Table 2. AGL Structure

Table 3. ADR/FAULT Output States

7.4.8.1 Overcurrent (OC) Protection With Current Limiting

The TAS5753MD device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored to prevent the output current from increasing beyond the overcurrent threshold defined in the Protection Circuitry Characteristics table.

If the output current increases beyond the overcurrent threshold, the device shuts down and the outputs transition to the off or high impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed. Current-limiting and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D shut down.

7.4.8.2 Overtemperature Protection

The TAS5753MD device has an overtemperature-protection system. If the device junction temperature exceeds 150°C (nominal), the device enters thermal shutdown, where all half-bridge outputs enter the high-impedance (Hi-Z) state, and ADR/FAULT asserts low if the device is configured to function as a fault output. The TAS5753MD device recovers automatically once the junction temperature of the device drops approximately 30°C.

7.4.8.3 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5753MD device fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach and 2.7 V, respectively. Although PVDD and AVDD are independently monitored. For PVDD, if the supply voltage drops below the UVP threshold, the protection feature immediately sets all half-bridge outputs to the high-impedance (Hi-Z) state and asserts ADR/FAULT low.

7.5.3.1 Stereo Mode

Stereo mode is the most common option for the TAS5753MD. TAS5753MD can be connected in 2.0 mode to drive stereo channels. Detailed application section regarding the stereo mode is discussed in the Stereo Bridge Tied Load Application section.

7.5.3.2 Mono Mode

Mono mode is described as the operation where the two BTL outputs of amplifier are placed in parallel with one another to provide increase in the output power capability. This mode is typically used to drive subwoofers, which require more power to drive larger loudspeakers with high-amplitude, low-frequency energy. Detailed application section regarding the mono mode is discussed in the Mono Parallel Bridge Tied Load Application section.

7.6.1.1 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 44. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5753MD device holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.

Figure 44. Typical I²C Sequence

No limit exists for the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 44.

The 7-bit address for the TAS5753MD device is 0101 010 (0x54) or 0101 011 (0x56) as defined by ADR/FAULT (external pulldown for 0x54 and pullup for 0x56).

7.6.1.2 I²C Slave Address

The ADR/FAULT is an input pin during power-up and after each toggle of RST, which is used to set the I²C sub-address of the device. The ADR/FAULT can also operate as a fault output after power-up is complete and the address has been latched in.

At power-up, and after each toggle of RST, the pin is read to determine its voltage level. If the pin is left floating, an internal pull-up will set the I²C sub-address to 0x56. This will also be the case if an external resistor is used to pull the pin up to AVDD. To set the sub-address to 0x54, an external resistor (specified in Typical Applications) must be connected to the system ground.

As mentioned, the pin can also be reconfigured as an output driver via I²C for fault monitoring. Use System Control Register 2 (0x05) to set ADR/FAULT pin to be used as a fault output during fault conditions.

7.6.1.3 Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses 0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-byte read/write operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. For example, if a write command is received for a biquad subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the received data is discarded.

Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. The TAS5753MD device also supports sequential I²C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I²C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5753MD device. For I²C sequential-write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted before a stop or start is transmitted determines how many subaddresses are written. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data is discarded.

7.6.1.4 Single-Byte Write

As shown in Figure 45, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the internal memory address being accessed. After receiving the address byte, the TAS5753MD device again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5753MD device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 45. Single-Byte Write Transfer

7.6.1.5 Multiple-Byte Write

A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 46. After receiving each data byte, the TAS5753MD device responds with an acknowledge bit.

Figure 46. Multiple-Byte Write Transfer

7.6.1.6 Single-Byte Read

As shown in Figure 47, a single-byte data-read transfer begins with the master device transmitting a start condition, followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5753MD address and the read/write bit, TAS5753MD device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5753MD address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5753MD device again responds with an acknowledge bit. Next, the TAS5753MD device transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.

Figure 47. Single-Byte Read Transfer

7.6.1.7 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the TAS5753MD device to the master device as shown in Figure 48. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 48. Multiple-Byte Read Transfer

7.6.2.1 Serial Data Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5753MD DAP accepts serial data in 16-bit, 20-bit, or 24-bit left-justified, right-justified, and I²S serial data formats.

7.6.2.2 I²S Timing

I²S timing uses LRCK to define when the data being transmitted is for the left channel and when the data is for the right channel. LRCK is low for the left channel and high for the right channel. A bit clock running at 32 × f_S, 48 × f_S, or 64 × f_S is used to clock in the data. A delay of one bit clock exists from the time the LRCK signal changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions.

NOTE:

All data presented in two's-complement form with MSB first.

Figure 49. I²S 64-f_S Format

NOTE:

All data presented in two's-complement form with MSB first.

Figure 50. I²S 48-f_S Format

NOTE:

All data presented in two's-complement form with MSB first.

Figure 51. I²S 32-f_S Format

7.6.2.3 Left-Justified

Left-justified (LJ) timing uses LRCK to define when the data being transmitted is for the left channel and when the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock running at 32 × f_S, 48 × f_S, or 64 × f_S is used to clock in the data. The first bit of data appears on the data lines at the same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.

NOTE:

All data presented in two's-complement form with MSB first.

Figure 52. Left-Justified 64-f_S Format

NOTE:

All data presented in two's-complement form with MSB first.

Figure 53. Left-Justified 48-f_S Format

NOTE:

All data presented in two's-complement form with MSB first.

Figure 54. Left-Justified 32-f_S Format

7.6.2.4 Right-Justified

Right-justified (RJ) timing uses LRCK to define when the data being transmitted is for the left channel and when the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock running at 32 × f_S, 48 × f_S, or 64 × f_S is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions.

All data presented in two's-complement form with MSB first.

Figure 55. Right-Justified 64-f_S Format

All data presented in two's-complement form with MSB first.

Figure 56. Right-Justified 48-f_S Format

All data presented in two's-complement form with MSB first.

Figure 57. Right-Justified 32-f_S Format

Table 4. Sample Calculation for 3.23 Format

Table 5. Sample Calculation for 9.17 Format

7.7.2.1 Clock Control Register (0x00)

The clocks and data rates are automatically determined by the TAS5753MD. The clock control register contains the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.

7.7.2.2 Device ID Register (0x01)

The device ID register contains the ID code for the firmware revision.

7.7.2.3 Error Status Register (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors.

Error definitions:

• MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK error: The number of SCLKs per LRCLK is changing.
• LRCLK error: LRCLK frequency is changing.
• Frame slip: LRCLK phase is drifting with respect to internal frame sync.

7.7.2.4 System Control Register 1 (0x03)

System control register 1 has several functions:

7.7.2.5 Serial Data Interface Register (0x04)

As shown in Table 10, the TAS5753MD supports nine serial data modes. The default is 24-bit, I²S mode.

7.7.2.6 System Control Register 2 (0x05)

When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute).

Ternary modulation is disabled by default. To enable ternary modulation, the following writes are required before bringing the system out of shutdown:

1. Set bit D3 of register 0x05 to 1.
2. Write the following ICD settings:
   1. 0x11= 80
   2. 0x12= 7C
   3. 0x13= 80
   4. 0x14 =7C
3. Set the input mux register as follows:
   1. 0x20 = 00 89 77 72

7.7.2.7 Soft Mute Register (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).

7.7.2.8 Volume Registers (0x07, 0x08, 0x09)

The volume register 0x07, 0x08, and 0x09 correspond to master volume, channel 1 volume, and channel 2 volume, respectively. Step size is 0.125 dB and volume registers are 2 bytes.

7.7.2.9 Volume Configuration Register (0x0E)

In two-band AGL, register 0x0A should be set to 0x30 and register 0x0E bits 6 and 5 should be set to 1.

7.7.2.10 Modulation Limit Register (0x10)

7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk, etc.) Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for the AD mode. If used in BD mode, then update these registers before coming out of all-channel shutdown.

7.7.2.12 PWM Shutdown Group Register (0x19)

Settings of this register determine which PWM channels are active. The functionality of this register is tied to the state of bit D5 in the system control register.

This register defines which channels belong to the shutdown group. If a 1 is set in the shutdown group register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is set to 0 in system control register 2, 0x05).

7.7.2.13 Start/Stop Period Register (0x1A)

This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I²S clock stability.

7.7.2.14 Oscillator Trim Register (0x1B)

The TAS5753MD PWM processor contains an internal oscillator to support autodetect of I²S clock rates. This reduces system cost because an external reference is not required. A reference resistor must be connected between pin 16 and 17, as shown in Table 19.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.

Note that trim must always be run following reset of the device.

7.7.2.15 BKND_ERR Register (0x1C)

When a back-end error signal is received from the internal power stage, the power stage is reset, stopping all PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 20 before attempting to re-start the power stage.

7.7.2.16 Input Multiplexer Register (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I²S audio to the internal channels.

7.7.2.17 PWM Output MUX Register (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin.

Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.

7.7.2.18 AGL Control Register (0x46)

7.7.2.19 PWM Switching Rate Control Register (0x4F)

PWM switching rate should be selected through the register 0x4F before coming out of all-channnel shutdown.

7.7.2.20 Bank Switch and EQ Control (0x50)