JAJSGO8F
July 2013 – February 2020
TAS5760M
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
機能ブロック図
10% THD+Nでの電力とPVDDとの関係
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Digital I/O Pins
6.5
Master Clock
6.6
Serial Audio Port
6.7
Protection Circuitry
6.8
Speaker Amplifier in All Modes
6.9
Speaker Amplifier in Stereo Bridge Tied Load (BTL) Mode
6.10
Speaker Amplifier in Mono Parallel Bridge Tied Load (PBTL) Mode
6.11
I²C Control Port
6.12
Typical Idle, Mute, Shutdown, Operational Power Consumption
6.13
Typical Characteristics (Stereo BTL Mode): fSPK_AMP = 384 kHz
6.14
Typical Characteristics (Stereo BTL Mode): fSPK_AMP = 768 kHz
6.15
Typical Characteristics (Mono PBTL Mode): fSPK_AMP = 384 kHz
6.16
Typical Characteristics (Mono PBTL Mode): fSPK_AMP = 768 kHz
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.2.1
Functional Block Diagram
8.3
Feature Description
8.3.1
Power Supplies
8.3.2
Speaker Amplifier Audio Signal Path
8.3.2.1
Serial Audio Port (SAP)
8.3.2.1.1
I²S Timing
8.3.2.1.2
Left-Justified
8.3.2.1.3
Right-Justified
8.3.2.2
DC Blocking Filter
8.3.2.3
Digital Boost and Volume Control
8.3.2.4
Digital Clipper
8.3.2.5
Closed-Loop Class-D Amplifier
8.3.3
Speaker Amplifier Protection Suite
8.3.3.1
Speaker Amplifier Fault Notification (SPK_FAULT Pin)
8.3.3.2
DC Detect Protection
8.4
Device Functional Modes
8.4.1
Hardware Control Mode
8.4.1.1
Speaker Amplifier Shut Down (SPK_SD Pin)
8.4.1.2
Serial Audio Port in Hardware Control Mode
8.4.1.3
Soft Clipper Control (SFT_CLIP Pin)
8.4.1.4
Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
8.4.1.5
Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
8.4.1.6
Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
8.4.1.7
Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
8.4.1.8
Considerations for Setting the Speaker Amplifier Gain Structure
8.4.1.8.1
Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
8.4.2
Software Control Mode
8.4.2.1
Speaker Amplifier Shut Down (SPK_SD Pin)
8.4.2.2
Serial Audio Port Controls
8.4.2.2.1
Serial Audio Port (SAP) Clocking
8.4.2.3
Parallel Bridge Tied Load Mode via Software Control
8.4.2.4
Speaker Amplifier Gain Structure
8.4.2.4.1
Speaker Amplifier Gain in Software Control Mode
8.4.2.4.2
Considerations for Setting the Speaker Amplifier Gain Structure
8.4.2.4.3
Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
8.4.2.5
I²C Software Control Port
8.4.2.5.1
Setting the I²C Device Address
8.4.2.5.2
General Operation of the I²C Control Port
8.4.2.5.3
Writing to the I²C Control Port
8.4.2.5.4
Reading from the I²C Control Port
8.5
Register Maps
8.5.1
Control Port Registers - Quick Reference
8.5.2
Control Port Registers - Detailed Description
8.5.2.1
Device Identification Register (0x00)
Table 9.
Device Identification Register Field Descriptions
8.5.2.2
Power Control Register (0x01)
Table 10.
Power Control Register Field Descriptions
8.5.2.3
Digital Control Register (0x02)
Table 11.
Digital Control Register Field Descriptions
8.5.2.4
Volume Control Configuration Register (0x03)
Table 12.
Volume Control Configuration Register Field Descriptions
8.5.2.5
Left Channel Volume Control Register (0x04)
Table 13.
Left Channel Volume Control Register Field Descriptions
8.5.2.6
Right Channel Volume Control Register (0x05)
Table 14.
Right Channel Volume Control Register Field Descriptions
8.5.2.7
Analog Control Register (0x06)
Table 15.
Analog Control Register Field Descriptions
8.5.2.8
Reserved Register (0x07)
8.5.2.9
Fault Configuration and Error Status Register (0x08)
Table 16.
Fault Configuration and Error Status Register Field Descriptions
8.5.2.10
Reserved Controls (9 / 0x09) - (15 / 0x0F)
8.5.2.11
Digital Clipper Control 2 Register (0x10)
Table 17.
Digital Clipper Control 2 Register Field Descriptions
8.5.2.12
Digital Clipper Control 1 Register (0x11)
Table 18.
Digital Clipper Control 1 Register Field Descriptions
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Stereo BTL Using Software Control
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Startup Procedures- Software Control Mode
9.2.1.2.2
Shutdown Procedures- Software Control Mode
9.2.1.2.3
Component Selection and Hardware Connections
9.2.1.2.3.1
I²C Pullup Resistors
9.2.1.2.3.2
Digital I/O Connectivity
9.2.1.2.4
Recommended Startup and Shutdown Procedures
9.2.1.3
Application Curves
9.2.2
Stereo BTL Using Software Control, 32-Pin DAP Package Option
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.2.1
Startup Procedures- Software Control Mode
9.2.2.2.2
Shutdown Procedures- Software Control Mode
9.2.2.2.3
Component Selection and Hardware Connections
9.2.2.2.3.1
I²C Pullup Resistors
9.2.2.2.3.2
Digital I/O Connectivity
9.2.2.2.4
Recommended Startup and Shutdown Procedures
9.2.2.3
Application Curve
9.2.3
Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
9.2.3.1
Design Requirements
9.2.3.2
Detailed Design Procedure
9.2.3.2.1
Startup Procedures - Hardware Control Mode
9.2.3.2.2
Shutdown Procedures - Hardware Control Mode
9.2.3.2.3
Digital I/O Connectivity
9.2.3.3
Application Curve
9.2.4
Mono PBTL Using Software Control, 32-Pin DAP Package Option
9.2.4.1
Design Requirements
9.2.4.2
Detailed Design Procedure
9.2.4.2.1
Startup Procedures - Software Control Mode
9.2.4.2.2
Shutdown Procedures - Software Control Mode
9.2.4.2.3
Component Selection and Hardware Connections
9.2.4.2.3.1
I²C Pull-Up Resistors
9.2.4.2.3.2
Digital I/O Connectivity
9.2.4.2.3.2.1
Application Curves
9.2.5
Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
9.2.5.1
Design Requirements
9.2.5.2
Detailed Design Procedure
9.2.5.2.1
Startup Procedures - Hardware Control Mode
9.2.5.2.2
Shutdown Procedures - Hardware Control Mode
9.2.5.2.3
Digital I/O Connectivity
9.2.5.2.4
Application Curves
10
Power Supply Recommendations
10.1
DVDD Supply
10.2
PVDD Supply
11
Layout
11.1
Layout Guidelines
11.1.1
General Guidelines for Audio Amplifiers
11.1.2
Importance of PVDD Bypass Capacitor Placement on PVDD Network
11.1.3
Optimizing Thermal Performance
11.1.3.1
Device, Copper, and Component Layout
11.1.3.2
Stencil Pattern
11.1.3.2.1
PCB Footprint and Via Arrangement
11.1.3.2.1.1
Solder Stencil
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
ドキュメントのサポート
12.1.1
関連資料
12.2
サポート・リソース
12.3
商標
12.4
静電気放電に関する注意事項
12.5
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DCA|48
MPDS044E
DAP|32
MPDS380A
サーマルパッド・メカニカル・データ
DCA|48
PPTD094K
DAP|32
PPTD001K
発注情報
jajsgo8f_oa
jajsgo8f_pm
9.2.5.2
Detailed Design Procedure