JAJSDH3A March   2016  – July 2017 TAS5782M

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Internal Pin Configurations
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation Characteristics
    7. 7.7  MCLK Timing
    8. 7.8  Serial Audio Port Timing - Slave Mode
    9. 7.9  Serial Audio Port Timing - Master Mode
    10. 7.10 I2C Bus Timing - Standard
    11. 7.11 I2C Bus Timing - Fast
    12. 7.12 SPK_MUTE Timing
    13. 7.13 Typical Characteristics
      1. 7.13.1 Bridge Tied Load (BTL) Configuration Curves
      2. 7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Parametric Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-on-Reset (POR) Function
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port
        1. 9.3.3.1 Clock Master Mode from Audio Rate Master Clock
        2. 9.3.3.2 Clock Master from a Non-Audio Rate Master Clock
        3. 9.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        4. 9.3.3.4 Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 9.3.3.4.1 Clock Generation using the PLL
          2. 9.3.3.4.2 PLL Calculation
            1. 9.3.3.4.2.1 Examples:
        5. 9.3.3.5 Serial Audio Port - Data Formats and Bit Depths
          1. 9.3.3.5.1 Data Formats and Master/Slave Modes of Operation
        6. 9.3.3.6 Input Signal Sensing (Power-Save Mode)
      4. 9.3.4 Enable Device
        1. 9.3.4.1 Example
      5. 9.3.5 Volume Control
        1. 9.3.5.1 DAC Digital Gain Control
          1. 9.3.5.1.1 Emergency Volume Ramp Down
      6. 9.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
      7. 9.3.7 Error Handling and Protection Suite
        1. 9.3.7.1 Device Overtemperature Protection
        2. 9.3.7.2 SPK_OUTxx Overcurrent Protection
        3. 9.3.7.3 DC Offset Protection
        4. 9.3.7.4 Internal VAVDD Undervoltage-Error Protection
        5. 9.3.7.5 Internal VPVDD Undervoltage-Error Protection
        6. 9.3.7.6 Internal VPVDD Overvoltage-Error Protection
        7. 9.3.7.7 External Undervoltage-Error Protection
        8. 9.3.7.8 Internal Clock Error Notification (CLKE)
      8. 9.3.8 GPIO Port and Hardware Control Pins
      9. 9.3.9 I2C Communication Port
        1. 9.3.9.1 Slave Address
        2. 9.3.9.2 Register Address Auto-Increment Mode
        3. 9.3.9.3 Packet Protocol
        4. 9.3.9.4 Write Register
        5. 9.3.9.5 Read Register
        6. 9.3.9.6 DSP Book, Page, and Register Update
          1. 9.3.9.6.1 Book and Page Change
          2. 9.3.9.6.2 Swap Flag
          3. 9.3.9.6.3 Example Use
    4. 9.4 Device Functional Modes
      1. 9.4.1 Serial Audio Port Operating Modes
      2. 9.4.2 Communication Port Operating Modes
      3. 9.4.3 Speaker Amplifier Operating Modes
        1. 9.4.3.1 Stereo Mode
        2. 9.4.3.2 Mono Mode
        3. 9.4.3.3 Master and Slave Mode Clocking for Digital Serial Audio Port
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 External Component Selection Criteria
      2. 10.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 10.1.3 Amplifier Output Filtering
      4. 10.1.4 Programming the TAS5782M
        1. 10.1.4.1 Resetting the TAS5782M Registers and Modules
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step One: Hardware Integration
          2. 10.2.1.2.2 Step Two: System Level Tuning
          3. 10.2.1.2.3 Step Three: Software Integration
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Mono (PBTL) Systems
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Step One: Hardware Integration
          2. 10.2.2.2.2 Step Two: System Level Tuning
          3. 10.2.2.2.3 Step Three: Software Integration
        3. 10.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
      3. 10.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
        1. 10.2.3.1 Advanced 2.1 System (Two TAS5782M devices)
        2. 10.2.3.2 Design Requirements
        3. 10.2.3.3 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 DVDD Supply
      2. 11.1.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
      1. 12.2.1 2.0 (Stereo BTL) System
      2. 12.2.2 Mono (PBTL) System
      3. 12.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
  13. 13Register Maps
    1. 13.1 Registers - Page 0
      1. 13.1.1  Register 1 (0x01)
      2. 13.1.2  Register 6 (0x06)
      3. 13.1.3  Register 7 (0x07)
      4. 13.1.4  Register 8 (0x08)
      5. 13.1.5  Register 9 (0x09)
      6. 13.1.6  Register 12 (0x0C)
      7. 13.1.7  Register 13 (0x0D)
      8. 13.1.8  Register 14 (0x0E)
      9. 13.1.9  Register 15 (0x0F)
      10. 13.1.10 Register 16 (0x10)
      11. 13.1.11 Register 17 (0x11)
      12. 13.1.12 Register 18 (0x12)
      13. 13.1.13 Register 20 (0x14)
      14. 13.1.14 Register 21 (0x15)
      15. 13.1.15 Register 22 (0x16)
      16. 13.1.16 Register 23 (0x17)
      17. 13.1.17 Register 24 (0x18)
      18. 13.1.18 Register 27 (0x1B)
      19. 13.1.19 Register 28 (0x1C)
      20. 13.1.20 Register 29 (0x1D)
      21. 13.1.21 Register 30 (0x1E)
      22. 13.1.22 Register 32 (0x20)
      23. 13.1.23 Register 33 (0x21)
      24. 13.1.24 Register 34 (0x22)
      25. 13.1.25 Register 37 (0x25)
      26. 13.1.26 Register 40 (0x28)
      27. 13.1.27 Register 41 (0x29)
      28. 13.1.28 Register 42 (0x2A)
      29. 13.1.29 Register 43 (0x2B)
      30. 13.1.30 Register 44 (0x2C)
      31. 13.1.31 Register 59 (0x3B)
      32. 13.1.32 Register 60 (0x3C)
      33. 13.1.33 Register 61 (0x3D)
      34. 13.1.34 Register 62 (0x3E)
      35. 13.1.35 Register 63 (0x3F)
      36. 13.1.36 Register 64 (0x40)
      37. 13.1.37 Register 65 (0x41)
      38. 13.1.38 Register 67 (0x43)
      39. 13.1.39 Register 68 (0x44)
      40. 13.1.40 Register 69 (0x45)
      41. 13.1.41 Register 70 (0x46)
      42. 13.1.42 Register 71 (0x47)
      43. 13.1.43 Register 72 (0x48)
      44. 13.1.44 Register 73 (0x49)
      45. 13.1.45 Register 74 (0x4A)
      46. 13.1.46 Register 75 (0x4B)
      47. 13.1.47 Register 76 (0x4C)
      48. 13.1.48 Register 78 (0x4E)
      49. 13.1.49 Register 79 (0x4F)
      50. 13.1.50 Register 83 (0x53)
      51. 13.1.51 Register 85 (0x55)
      52. 13.1.52 Register 86 (0x56)
      53. 13.1.53 Register 87 (0x57)
      54. 13.1.54 Register 88 (0x58)
      55. 13.1.55 Register 91 (0x5B)
      56. 13.1.56 Register 92 (0x5C)
      57. 13.1.57 Register 93 (0x5D)
      58. 13.1.58 Register 94 (0x5E)
      59. 13.1.59 Register 95 (0x5F)
      60. 13.1.60 Register 108 (0x6C)
      61. 13.1.61 Register 119 (0x77)
      62. 13.1.62 Register 120 (0x78)
    2. 13.2 Registers - Page 1
      1. 13.2.1 Register 1 (0x01)
      2. 13.2.2 Register 2 (0x02)
      3. 13.2.3 Register 6 (0x06)
      4. 13.2.4 Register 7 (0x07)
      5. 13.2.5 Register 9 (0x09)
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デバイスの項目表記
      2. 14.1.2 開発サポート
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section details the information required to configure the device for several popular configurations and provides guidance on integrating the TAS5782M device into the larger system.

10.1.1 External Component Selection Criteria

The Supporting Component Requirements table in each application description section lists the details of the supporting required components in each of the System Application Schematics.

Where possible, the supporting component requirements have been consolidated to minimize the number of unique components which are used in the design. Component list consolidation is a method to reduce the number of unique part numbers in a design, to ease inventory management, and to reduce the manufacturing steps during board assembly. For this reason, some capacitors are specified at a higher voltage than what would normally be required. An example of this is a 50-V capacitor may be used for decoupling of a 3.3-V power supply net.

In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of that value into a single component type. Similarly, several unique resistors that have all the same size and value but different power ratings can be consolidated by using the highest rated power resistor for each instance of that resistor value.

While this consolidation can seem excessive, the benefits of having fewer components in the design can far outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of the capacitors should be 1.5 times to 1.75 times the power dissipated in it during normal use case.

10.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing

Because the layout is important to the overall performance of the circuit, the package size of the components shown in the component list was intentionally chosen to allow for proper board layout, component placement, and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane extensions from the TAS5782M device and into to the surrounding copper for increased heat-sinking of the device. While components may be offered in smaller or larger package sizes, it is highly recommended that the package size remain identical to the size used in the application circuit as shown. This consistency ensures that the layout and routing can be matched very closely, which optimizes thermal, electromagnetic, and audio performance of the TAS5782M device in circuit in the final system.

10.1.3 Amplifier Output Filtering

The TAS5782M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive element L and a capacitive element C to make up the 2-pole filter.

The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a simple ferrite bead or a ferrite bead plus a capacitor can replace the traditional large inductor and capacitor that are commonly used. In other high-power applications, large toroid inductors are required for maximum power and film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter Design (SLOA119) for a detailed description on the proper component selection and design of an L-C filter based upon the desired load and response.

10.1.4 Programming the TAS5782M

The TAS5782M device includes an I2C compatible control port to configure the internal registers of the TAS5782M device. The control console software provided by TI is required to configure the device. More details regarding programming steps, and a few important notes are available below and also in the design examples that follow.

10.1.4.1 Resetting the TAS5782M Registers and Modules

The TAS5782M device has several methods by which the device can reset the register, interpolation filters, and DAC modules. The registers offer the flexibility to do these in or out of shutdown as well as in or out of standby. However, there can be issues if the reset bits are toggled in certain illegal operation modes.

Any of the following routines can be used with no issue:

  • Reset Routine 1
    • Place device in Standby
    • Reset modules
  • Reset Routine 2
    • Place device in Standby + Power Down
    • Reset registers
  • Reset Routine 3
    • Place device in Power Down
    • Reset registers
  • Reset Routine 4
    • Place device in Standby
    • Reset registers
  • Reset Routine 5
    • Place device in Standby + Power Down
    • Reset modules + Reset registers
  • Reset Routine 6
    • Place device in Power Down
    • Reset modules + Reset registers
  • Reset Routine 7
    • Place device in Standby
    • Reset modules + Reset registers

Two reset routines are not supported and should be avoided. If used, they can cause the device to become unresponsive. These unsupported routines are shown below.

  • Unsupported Reset Routine 1 (do not use)
    • Place device in Standby + Power Down
    • Reset modules
  • Unsupported Reset Routine 2 (do not use)
    • Place device in Power Down
    • Reset modules

10.2 Typical Applications

10.2.1 2.0 (Stereo BTL) System

For the stereo (BTL) PCB layout, see Figure 85.

A 2.0 system refers to a system in which there are two full range speakers without a separate amplifier path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated based upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered 2.0.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the audio for the left channel and the other channel containing the audio for the right channel. While certainly the two channels can contain any two audio channels, such as two surround channels of a multi-channel speaker system, the most popular occurrence in two channels systems is a stereo pair.

Figure 80 shows the 2.0 (Stereo BTL) system application.

TAS5782M typ_app_stereo_btl_20_slaseg8.gif Figure 80. 2.0 (Stereo BTL) System Application Schematic

10.2.1.1 Design Requirements

  • Power supplies:
    • 3.3-V supply
    • 5-V to 24-V supply
  • Communication: host processor serving as I2C compliant master
  • External memory (such as EEPROM and flash) used for coefficients

The requirements for the supporting components for the TAS5782M device in a Stereo 2.0 (BTL) system is provided in Table 21.

Table 21. Supporting Component Requirements for Stereo 2.0 (BTL) Systems

REFERENCE
DESIGNATOR		 VALUE SIZE DETAILED DESCRIPTION
U100 TAS5782M 48 Pin TSSOP Digital-input, closed-loop class-D amplifier
R100 See the Adjustable Amplifier Gain and Switching Frequency Selection section 0402 1%, 0.063 W
R101 0402 1%, 0.063 W
L100, L101, L102, L103 See the Amplifier Output Filtering section
C100, C121 0.1 µF 0402 Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C104, C108, C111, C115 0.22 µF 0603 Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C109, C110, C116, C117 0.68 µF 0805 Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C103 1 µF 0603
(this body size chosen to aid in trace routing)		 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 16 V
C105, C118, C119, C120 1 µF 0402 Ceramic, 1 µF, 6.3V, ±10%, X5R
C106, C107, C113, C114 2.2 µF 0402 Ceramic, 2.2 µF, ±10%, X5R
At a minimum, voltage rating must be > 10V, however higher voltage caps have been shown to have better stability under DC bias. Refer to the guidance provided in the TAS5782M for suggested values.
C101, C102, C122, C123 22 µF 0805 Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Step One: Hardware Integration

  • Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
  • Following the recommended component placement, board layout, and routing given in the example layout above, integrate the device and its supporting components into the system PCB file.
    • The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they are given precedent as design trade-offs are made is recommended.
    • For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is necessary, go to the E2E forum to request a layout review.

10.2.1.2.2 Step Two: System Level Tuning

  • Use the TAS5782MEVM evaluation module and the PPC3 app to configure the desired device settings.

10.2.1.2.3 Step Three: Software Integration

  • Use the End System Integration feature of the PPC3 app to generate a baseline configuration file.
  • Generate additional configuration files based upon operating modes of the end-equipment and integrate static configuration information into initialization files.
  • Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the main system program.

10.2.1.3 Application Curves

Table 22 shows the application specific performance plots for Stereo 2.0 (BTL) systems.

Table 22. Relevant Performance Plots

PLOT TITLE FIGURE NUMBER
Output Power vs PVDD Figure 23
THD+N vs Frequency, VPVDD = 12 V Figure 24
THD+N vs Frequency, VPVDD = 15 V Figure 25
THD+N vs Frequency, VPVDD = 18 V Figure 26
THD+N vs Frequency, VPVDD = 24 V Figure 27
THD+N vs Power, VPVDD = 12 V Figure 28
THD+N vs Power, VPVDD = 15 V Figure 29
THD+N vs Power, VPVDD = 18 V Figure 30
THD+N vs Power, VPVDD = 24 V Figure 31
Idle Channel Noise vs PVDD Figure 32
Efficiency vs Output Power Figure 33
DVDD PSRR vs. Frequency Figure 39
AVDD PSRR vs. Frequency Figure 40
CPVDD PSRR vs. Frequency Figure 41

10.2.2 Mono (PBTL) Systems

For the mono (PBTL) PCB layout, see Figure 87.

A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5782M device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while the on-resistance is approximately halved.

The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed together and sent through a low-pass filter to create a single audio signal which contains the low frequency information of the two channels. Conversely, advanced digital signal processing can create a low-frequency signal for a multichannel system, with audio processing which is specifically targeted on low-frequency effects.

Because low-frequency signals are not perceived as having a direction (at least to the extent of high-frequency signals) it is common to reproduce the low-frequency content of a stereo signal that is sent to two separate channels. This configuration pairs one device in Mono PBTL configuration and another device in Stereo BTL configuration in a single system called a 2.1 system. The Mono PBTL configuration is detailed in the 2.1 (Stereo BTL + External Mono Amplifier) Systems section. shows the Mono (PBTL) system application

TAS5782M typ_app_mono_pbtl_slaseg8.gif Figure 81. Mono (PBTL) System Application Schematic

10.2.2.1 Design Requirements

  • Power supplies:
    • 3.3-V supply
    • 5-V to 24-V supply
  • Communication: Host processor serving as I2C compliant master
  • External memory (EEPROM, flash, and others) used for coefficients.

The requirements for the supporting components for the TAS5782M device in a Mono (PBTL) system is provided in Table 23.

Table 23. Supporting Component Requirements for Mono (PBTL) Systems

REFERENCE
DESIGNATOR		 VALUE SIZE DETAILED DESCRIPTION
U200 TAS5782M 48 Pin TSSOP Digital-input, closed-loop class-D amplifier with 96kHz processing
R200 See the Adjustable Amplifier Gain and Switching Frequency Selection section 0402 1%, 0.063 W
R201 0402 1%, 0.063 W
R202 0402 1%, 0.063 W
L200, L201 See theAmplifier Output Filtering section
C216, C201 0.1 µF 0402 Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C208, C209, C214, C215 0.22 µF 0603 Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C220, C221 0.68 µF 0805 Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C200 1 µF 0603
(this body size chosen to aid in trace routing)		 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 16 V
C205, C211, C213, C212 1 µF 0402 Ceramic, 1 µF, 6.3 V, ±10%, X5R
C202, C217, C352, C367 1 µF 0805
(this body size chosen to aid in trace routing)		 Ceramic, 1 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
C206, C207 2.2 µF 0402 Ceramic, 2.2 µF, ±10%, X5R
At a minimum, voltage rating must be > 10V, however higher voltage caps have been shown to have better stability under DC bias please follow the guidance provided in the TAS5782M for suggested values.
C203, C218 22 µF 0805 Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
C204, C219 390 µF 10 × 10 Aluminum, 390 µF, ±20%, 0.08-Ω
Voltage rating must be > 1.45 × VPVDD Anticipating that this application circuit would be followed for higher power subwoofer applications, these capacitors are added to provide local current sources for low-frequency content. These capacitors can be reduced or even removed based upon final system testing, including critical listening tests when evaluating low-frequency designs.

10.2.2.2 Detailed Design Procedure

10.2.2.2.1 Step One: Hardware Integration

  • Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
  • Following the recommended component placement, board layout, and routing given in the example layout above, integrate the device and its supporting components into the system PCB file.
    • The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they are given precedent as design trade-offs are made is recommended.
    • For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is necessary, go to the E2E forum to request a layout review.

10.2.2.2.2 Step Two: System Level Tuning

  • Use the TAS5782MEVM evaluation module and the PPC3 app to configure the desired device settings.

10.2.2.2.3 Step Three: Software Integration

  • Use the End System Integration feature of the PPC3 app to generate a baseline configuration file.
  • Generate additional configuration files based upon operating modes of the end-equipment and integrate static configuration information into initialization files.
  • Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the main system program.

10.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems

Table 24 shows the application specific performance plots for Mono (PBTL) Systems

Table 24. Relevant Performance Plots

PLOT TITLE FIGURE NUMBER
Output Power vs PVDD Figure 47
THD+N vs Frequency, VPVDD = 12 V Figure 48
THD+N vs Frequency, VPVDD = 15 V Figure 49
THD+N vs Frequency, VPVDD = 18 V Figure 50
THD+N vs Frequency, VPVDD = 24 V Figure 51
THD+N vs Power, VPVDD = 12 V Figure 52
THD+N vs Power, VPVDD = 15 V Figure 53
THD+N vs Power, VPVDD = 18 V Figure 54
THD+N vs Power, VPVDD = 24 V Figure 55
Idle Channel Noise vs PVDD Figure 56
Efficiency vs Output Power Figure 57

10.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems

Figure 89 shows the PCB Layout for the 2.1 System.

To increase the low-frequency output capabilities of an audio system, a single subwoofer can be added to the system. Because the spatial clues for audio are predominately higher frequency than that reproduced by the subwoofer, often a single subwoofer can be used to reproduce the low frequency content of several other channels in the system. This is frequently referred to as a dot one system. A stereo system with a subwoofer is referred to as a 2.1 (two-dot-one), a 3 channel system with subwoofer is referred to as a 3.1 (three-dot-one), a popular surround system with five speakers and one subwoofer is referred to as a 5.1, and so on.

10.2.3.1 Advanced 2.1 System (Two TAS5782M devices)

In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was done in the high-frequency channels. To accomplish this, two TAS5782M devices are used — one for the high frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can be sent from the TAS5782M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept the same digital input as the stereo, which might come from a central systems processor. Figure 82 shows the 2.1 (Stereo BTL + External Mono Amplifier) system application.

TAS5782M typ_app_21_stereo_btl_mono_pbtl_slaseg8.gif Figure 82. 2.1 (Stereo BTL + External Mono Amplifier) Application Schematic

10.2.3.2 Design Requirements

  • Power supplies:
    • 3.3-V supply
    • 5-V to 24-V supply
  • Communication: Host processor serving as I2C compliant master
  • External memory (EEPROM, flash, and others) used for coefficients.

The requirements for the supporting components for the TAS5782M device in a 2.1 (Stereo BTL + External Mono Amplifier) system is provided in Table 25.

Table 25. Supporting Component Requirements for 2.1 (Stereo BTL + External Mono Amplifier) Systems

REFERENCE
DESIGNATOR		 VALUE SIZE DETAILED DESCRIPTION
U300 TAS5782M 48 Pin TSSOP Digital-input, closed-loop class-D amplifier 96kHz Processing
R300, R350 See the Adjustable Amplifier Gain and Switching Frequency Selection section 0402 1%, 0.063 W
R301, R351 0402 1%, 0.063 W
R352 0402 1%, 0.063 W
L300, L301, L302, L303 See the Amplifier Output Filtering section
L350, L351
C394, C395, C396, C397, C398, C399 0.01 µF 0603 Ceramic, 0.01 µF, 50 V, +/-10%, X7R
C300, C321, C351, C366 0.1 µF 0402 Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C304, C308, C311, C315, C358, C359, C364, C365 0.22 µF 0603 Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C309, C310, C316, C317, C370, C371 0.68 µF 0805 Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C303, C350, C312, C360 1 µF 0603 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C305, C318, C319, C320, C355, C361, C363, C312, C362 1 µF 0402 Ceramic, 1 µF, 6.3V, ±10%, X5R
C352, C367 1 µF 0805 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C306, C307, C313, C314, C356, C357, 2.2 µF 0402 Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
C301, C302, C322, C323, C353, C368 22 µF 0805 Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
C354, C369 390 µF 10 × 10 Aluminum, 390 µF, ±20%, 0.08 Ω
Voltage rating must be > 1.45 × VPVDD

10.2.3.3 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems

Table 26 shows the application specific performance plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems

Table 26. Relevant Performance Plots

DEVICE PLOT TITLE FIGURE NUMBER
U300 Output Power vs PVDD Figure 23
THD+N vs Frequency, VPVDD = 12 V Figure 24
THD+N vs Frequency, VPVDD = 15 V Figure 25
THD+N vs Frequency, VPVDD = 18 V Figure 26
THD+N vs Frequency, VPVDD = 24 V Figure 27
THD+N vs Power, VPVDD = 12 V Figure 28
THD+N vs Power, VPVDD = 15 V Figure 29
THD+N vs Power, VPVDD = 18 V Figure 30
THD+N vs Power, VPVDD = 24 V Figure 31
Idle Channel Noise vs PVDD Figure 32
Efficiency vs Output Power Figure 33
U301 PVDD PSRR vs Frequency Figure 38
Output Power vs PVDD Figure 47
THD+N vs Frequency, VPVDD = 12 V Figure 48
THD+N vs Frequency, VPVDD = 15 V Figure 49
THD+N vs Frequency, VPVDD = 18 V Figure 50
THD+N vs Frequency, VPVDD = 24 V Figure 51
THD+N vs Power, VPVDD = 12 V Figure 52
THD+N vs Power, VPVDD = 15 V Figure 53
THD+N vs Power, VPVDD = 18 V Figure 54
THD+N vs Power, VPVDD = 24 V Figure 55
Idle Channel Noise vs PVDD Figure 56
Efficiency vs Output Power Figure 57
U300
and
U301		 DVDD PSRR vs. Frequency Figure 39
AVDD PSRR vs. Frequency Figure 40
CPVDD PSRR vs. Frequency Figure 41
Powerdown Current Draw vs. PVDD Figure 47