JAJSDH3 データシート

JAJSDH3A March 2016 – July 2017 TAS5782M

PRODUCTION DATA.

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13 Register Maps

13.1 Registers - Page 0

13.1.1 Register 1 (0x01)

Figure 90. Register 1 (0x01)

7	6	5	4	3	2	1	0
Reserved			RSTM	Reserved			RSTR
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. Register 1 (0x01) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved			Reserved
4	RSTM	R/W	0	Reset Modules – This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit is auto cleared and can be set only in standby mode. 0: Normal 1: Reset modules
3-1	Reserved			Reserved
0	RSTR	R/W	0	Reset Registers – This bit resets the mode registers back to their initial values. The RAM content is not cleared, but the execution source will be back to ROM. This bit is auto cleared and must be set only when the DAC is in standby mode (resetting registers when the DAC is running is prohibited and not supported). 0: Normal 1: Reset mode registers

Figure 91. Register 2 (0x02)

7	6	5	4	3	2	1	0
DSPR	Reserved		RQST	Reserved			RQPD
R/W	R/W		R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. Register 2 (0x02) Field Descriptions

Bit	Field	Type	Reset	Description
7	DSPR	R/W	1	DSP reset – When the bit is made 0, DSP will start powering up and send out data. This needs to be made 0 only after all the input clocks are (ASI,MCLK,PLLCLK) are settled so that DMA channels do not go out of sync. 0: Normal operation 1: Reset the DSP
6-5	Reserved	R/W		Reserved
4	RQST	R/W	0	Standby Request – When this bit is set, the DAC will be forced into a system standby mode, which is also the mode the system enters in the case of clock errors. In this mode, most subsystems will be powered down but the charge pump and digital power supply. 0: Normal operation 1: Standby mode
3-1	Reserved	R/W		Reserved
0	RQPD	R/W	0	Powerdown Request – When this bit is set, the DAC will be forced into powerdown mode, in which the power consumption would be minimum as the charge pump is also powered down. However, it will take longer to restart from this mode. This mode has higher precedence than the standby mode, i.e. setting this bit along with bit 4 for standby mode will result in the DAC going into powerdown mode. 0: Normal operation 1: Powerdown mode

Figure 92. Register 3 (0x03)

7	6	5	4	3	2	1	0
Reserved			RQML	Reserved			RQMR
RO			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. Register 3 (0x03) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	RO		Reserved
4	RQML	R/W	0	Mute Left Channel – This bit issues soft mute request for the left channel. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute
3-1	Reserved	R/W		Reserved
0	RQMR	R/W	0	Mute Right Channel – This bit issues soft mute request for the right channel. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute

Figure 93. Register 4 (0x04)

7	6	5	4	3	2	1	0
Reserved			PLCK	Reserved			PLLE
R/W			R	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. Register 4 (0x04) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4	PLCK	R	0	PLL Lock Flag – This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the PLL is not locked. 0: The PLL is locked 1: The PLL is not locked
3-1	Reserved	R/W		Reserved
0	PLLE	R/W	1	PLL Enable – This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the MCLK. 0: Disable PLL 1: Enable PLL

13.1.2 Register 6 (0x06)

Figure 94. Register 6 (0x06)

7	6	5	4	3	2	1	0
Reserved				DBPG	Reserved
R/W				R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. Register 6 (0x06) Field Descriptions

Bit	Field	Type	Description
7-4	Reserved		Reserved
3	DBPG	R/W	Page auto increment disable – Disable page auto increment mode. for non -zero books. When end of page is reached it goes back to 8th address location of next page when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in older part. 0: Enable Page auto increment 1: Disable Page auto increment
2-0	Reserved	R/W	Reserved

13.1.3 Register 7 (0x07)

Figure 95. Register 7 (0x07)

7	6	5	4	3	2	1	0
Reserved			DEMP	Reserved			SDSL
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. Register 7 (0x07) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	DEMP	R/W	0	De-Emphasis Enable – This bit enables or disables the de-emphasis filter. The default coefficients are for 44.1 kHz sampling rate, but can be changed by reprogramming the appropriate coeffients in RAM. 0: De-emphasis filter is disabled 1: De-emphasis filter is enabled
3-1	Reserved	R/W	0	Reserved
0	SDSL	R/W	1	SDOUT Select – This bit selects what is being output as SDOUT via GPIO pins. 0: SDOUT is the DSP output (post-processing) 1: SDOUT is the DSP input (pre-processing)

13.1.4 Register 8 (0x08)

Figure 96. Register 8 (0x08)

7	6	5	4	3	2	1	0
Reserved		G2OE	MUTEOE	G0OE	Reserved
R/W		R/W	R/W	R/W	R/W

Table 33. Register 8 (0x08) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W		Reserved
5	G2OE	R/W	0	GPIO2 Output Enable – This bit sets the direction of the GPIO2 pin 0: GPIO2 is input 1: GPIO2 is output
4	MUTEOE	R/W	0	MUTE Control Enable – This bit sets an enable of MUTE control from PCM to TPA 0: MUTE control disable 1: MUTE control enable
3	G0OE	R/W	0	GPIO0 Output Enable – This bit sets the direction of the GPIO0 pin 0: GPIO0 is input 1: GPIO0 is output
2-0	Reserved	R/W	0	Reserved

13.1.5 Register 9 (0x09)

Figure 97. Register 9 (0x09)

7	6	5	4	3	2	1	0
Reserved		SCLKP	SCLKO	Reserved			LRCLKFSO
R/W		R/W	R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. Register 9 (0x09) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved			Reserved
5	SCLKP	R/W	0	SCLK Polarity – This bit sets the inverted SCLK mode. In inverted SCLK mode, the DAC assumes that the LRCLK and DIN edges are aligned to the rising edge of the SCLK. Normally they are assumed to be aligned to the falling edge of the SCLK. 0: Normal SCLK mode 1: Inverted SCLK mode
4	SCLKO	R/W	0	SCLK Output Enable – This bit sets the SCLK pin direction to output for I2S master mode operation. In I2S master mode the PCM51xx outputs the reference SCLK and LRCLK, and the external source device provides the DIN according to these clocks. Use P0-R32 to program the division factor of the MCLK to yield the desired SCLK rate (normally 64 FS) 0: SCLK is input (I2S slave mode) 1: SCLK is output (I2S master mode)
3-1	Reserved			Reserved
0	LRKO	R/W	0	LRCLK Output Enable – This bit sets the LRCLK pin direction to output for I2S master mode operation. In I2S master mode the PCM51xx outputs the reference SCLK and LRCLK, and the external source device provides the DIN according to these clocks. Use P0-R33 to program the division factor of the SCLK to yield 1 FS for LRCLK. 0: LRCLK is input (I2S slave mode) 1: LRCLK is output (I2S master mode)

13.1.6 Register 12 (0x0C)

Figure 98. Register 12 (0x0C)

7	6	5	4	3	2	1	0
Reserved						RSCLK	RLRK
R/W						R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. Register 12 (0x0C) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W		Reserved
1	RSCLK	R/W	0	Master Mode SCLK Divider Reset – This bit, when set to 0, will reset the MCLK divider to generate SCLK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. 0: Master mode SCLK clock divider is reset 1: Master mode SCLK clock divider is functional
0	RLRK	R/W	1	Master Mode LRCLK Divider Reset – This bit, when set to 0, will reset the SCLK divider to generate LRCLK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. 0: Master mode LRCLK clock divider is reset 1: Master mode LRCLK clock divider is functional

13.1.7 Register 13 (0x0D)

Figure 99. Register 13 (0x0D)

7	6	5	4	3	2	1	0
Reserved			SREF	Reserved	SDSP
R/W			R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. Register 13 (0x0D) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4	SREF	R/W	0	DSP clock source – This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode. 0: The PLL reference clock is MCLK 1: The PLL reference clock is SCLK 010: The PLL reference clock is oscillator clock 011: The PLL reference clock is GPIO (selected using P0-R18) Others: Reserved (PLL reference is muted)
3	Reserved	R/W		Reserved
2-0	SDSP	R/W	0	DAC clock source – These bits select the source clock for DSP clock divider. 000: Master clock (PLL/MCLK and OSC auto-select) 001: PLL clock 010: OSC clock 011: MCLK clock 100: SCLK clock 101: GPIO (selected using P0-R16) Others: Reserved (muted)

13.1.8 Register 14 (0x0E)

Figure 100. Register 14 (0x0E)

7	6	5	4	3	2	1	0
Reserved	SDAC			Reserved	SOSR
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. Register 14 (0x0E) Field Descriptions

Bit	Field	Type	Description
7	Reserved	R/W	Reserved
6-4	SDAC	R/W	DAC clock source – These bits select the source clock for DAC clock divider. 000: Master clock (PLL/MCLK and OSC auto-select) 001: PLL clock 010: OSC clock 011: MCLK clock 100: SCLK clock 101: GPIO (selected using P0-R16) Others: Reserved (muted)
3	Reserved	R/W	Reserved
2-0	SOSR	R/W	OSR clock source – These bits select the source clock for OSR clock divider. 000: DAC clock 001: Master clock (PLL/MCLK and OSC auto-select) 010: PLL clock 011: OSC clock 100: MCLK clock 101: SCLK clock 110: GPIO (selected using P0-R17) Others: Reserved (muted)

13.1.9 Register 15 (0x0F)

Figure 101. Register 15 (0x0F)

7	6	5	4	3	2	1	0
Reserved					SNCP
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. Register 15 (0x0F) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W		Reserved
2-0	SNCP	R/W	0	NCP clock source – These bits select the source clock for CP clock divider. 000: DAC clock 001: Master clock (PLL/MCLK and OSC auto-select) 010: PLL clock 011: OSC clock 100: MCLK clock 101: SCLK clock 110: GPIO (selected using P0-R17) Others: Reserved (muted)

13.1.10 Register 16 (0x10)

Figure 102. Register 16 (0x10)

7	6	5	4	3	2	1	0
Reserved	GDSP			Reserved	GDAC
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. Register 16 (0x10) Field Descriptions

Bit	Field	Type	Description
7	Reserved	R/W	Reserved
6-4	GDSP	R/W	GPIO Source for uCDSP clk – These bits select the GPIO pins as clock input source when GPIO is selected as DSP clock divider source. 000: N/A 001: N/A 010: N/A 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)
3	Reserved	R/W	Reserved
2-0	GDAC	R/W	GPIO Source for DAC clk – These bits select the GPIO pins as clock input source when GPIO is selected as DAC clock divider source. 000: N/A 001: N/A 010: N/A 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)

13.1.11 Register 17 (0x11)

Figure 103. Register 17 (0x11)

7	6	5	4	3	2	1	0
Reserved	GNCP			Reserved	GOSR
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. Register 17 (0x11) Field Descriptions

Bit	Field	Type	Description
7	Reserved	R/W	Reserved
6-4	GNCP	R/W	GPIO Source for NCP clk – These bits select the GPIO pins as clock input source when GPIO is selected as CP clock divider source 000: N/A 001: N/A 010: Reserved 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)
3	Reserved	R/W	Reserved
2-0	GOSR	R/W	GPIO Source for OSR clk – These bits select the GPIO pins as clock input source when GPIO is selected as OSR clock divider source. 000: N/A 001: N/A 010: Reserved 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)

13.1.12 Register 18 (0x12)

Figure 104. Register 18 (0x12)

7	6	5	4	3	2	1	0
Reserved					GREF
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. Register 18 (0x12) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W	0	Reserved
2-0	GREF	R/W	0	GPIO Source for PLL reference clk – These bits select the GPIO pins as clock input source when GPIO is selected as the PLL reference clock source. 000: N/A 001: N/A 010: Reserved 011: GPIO0 100: N/A 101: GPIO2 Others: Reserved (muted)

13.1.13 Register 20 (0x14)

Figure 105. Register 20 (0x14)

7	6	5	4	3	2	1	0
Reserved				PPDV
R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. Register 20 (0x14) Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved	R/W	0	Reserved
3-0	PPDV	R/W	0	PLL P – These bits set the PLL divider P factor. These bits are ignored in clock auto set mode. 0000: P=1 0001: P=2 ... 1110: P=15 1111: Prohibited (do not set this value)

13.1.14 Register 21 (0x15)

Figure 106. Register 21 (0x15)

7	6	5	4	3	2	1	0
Reserved		PJDV
R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 43. Register 21 (0x15) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved		0	Reserved
5-0	PJDV	R/W	001000	PLL J – These bits set the J part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. 000000: Prohibited (do not set this value) 000001: J=1 000010: J=2 ... 111111: J=63

Bit

Field

Type

Reset

Description

7-6

Reserved

5-0

PJDV

R/W

001000

PLL J – These bits set the J part of the overall PLL multiplication factor J.D * R.

These bits are ignored in clock auto set mode.

000000: Prohibited (do not set this value)
000001: J=1
000010: J=2
...
111111: J=63

13.1.15 Register 22 (0x16)

Figure 107. Register 22 (0x16)

7	6	5	4	3	2	1	0
Reserved		PDDV
R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 44. Register 22 (0x16) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W		Reserved
5-0	PDDV	R/W	0	PLL D (MSB) – These bits set the D part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. 0 (in decimal): D=0000 1 (in decimal): D=0001 ... 9999 (in decimal): D=9999 Others: Prohibited (do not set)

13.1.16 Register 23 (0x17)

Figure 108. Register 23 (0x17)

7	6	5	4	3	2	1	0
PDDV
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 45. Register 23 (0x17) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PDDV	R/W	0	PLL D (LSB) – These bits set the D part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. 0 (in decimal): D=0000 1 (in decimal): D=0001 ... 9999 (in decimal): D=9999 Others: Prohibited (do not set)

13.1.17 Register 24 (0x18)

Figure 109. Register 24 (0x18)

7	6	5	4	3	2	1	0
Reserved				PRDV
R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 46. Register 24 (0x18) Field Descriptions

Bit	Field	Type	Reset	Description
7-4	Reserved	R/W		Reserved
3-0	PRDV	R/W	0	PLL R – These bits set the R part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode. 0000: R=1 0001: R=2 ... 1111: R=16

13.1.18 Register 27 (0x1B)

Figure 110. Register 27 (0x1B)

7	6	5	4	3	2	1	0
Reserved	DDSP
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 47. Register 27 (0x1B) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6-0	DDSP	R/W	0	DSP Clock Divider – These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128

13.1.19 Register 28 (0x1C)

Figure 111. Register 28 (0x1C)

7	6	5	4	3	2	1	0
Reserved	DDAC
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 48. Register 28 (0x1C) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved			Reserved
6-4	DDAC	R/W	0	DAC Clock Divider – These bits set the source clock divider value for the DAC clock. These bits are ignored in clock auto set mode. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128
3-0	DDAC	R/W	1

13.1.20 Register 29 (0x1D)

Figure 112. Register 29 (0x1D)

7	6	5	4	3	2	1	0
Reserved	DNCP
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 49. Register 29 (0x1D) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved			Reserved
6-2	DNCP	R/W	0	NCP Clock Divider – These bits set the source clock divider value for the CP clock. These bits are ignored in clock auto set mode. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128
1-0	DNCP	R/W	1

13.1.21 Register 30 (0x1E)

Figure 113. Register 30 (0x1E)

7	6	5	4	3	2	1	0
Reserved	DOSR
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 50. Register 30 (0x1E) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved			Reserved
6-4	DOSR	R/W	0	OSR Clock Divider – These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128
3-0	DOSR	R/W	1

13.1.22 Register 32 (0x20)

Figure 114. Register 32 (0x20)

7	6	5	4	3	2	1	0
Reserved	DSCLK
R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 51. Register 32 (0x20) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6-0	DSCLK	R/W	0	Master Mode SCLK Divider – These bits set the MCLK divider value to generate I2S master SCLK clock. 0000000: Divide by 1 0000001: Divide by 2 ... 1111111: Divide by 128

13.1.23 Register 33 (0x21)

Figure 115. Register 33 (0x21)

7	6	5	4	3	2	1	0
DLRK
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 52. Register 33 (0x21) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLRK	R/W	0	Master Mode LRCLK Divider – These bits set the I2S master SCLK clock divider value to generate I2S master LRCLK clock 00000000: Divide by 1 00000001: Divide by 2 ... 11111111: Divide by 256

13.1.24 Register 34 (0x22)

Figure 116. Register 34 (0x22)

7	6	5	4	3	2	1	0
Reserved			I16E	Reserved	FSSP	FSSP
R/W			R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 53. Register 34 (0x22) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4	I16E	R/W	0	16x Interpolation – This bit enables or disables the 16x interpolation mode 0: 8x interpolation 1: 16x interpolation
3	Reserved	R/W		Reserved
2	FSSP	R/W	1	FS Speed Mode – These bits select the FS operation mode, which must be set according to the current audio sampling rate. These bits are ignored in clock auto set mode. 000: Reserved 001: Reserved 010: Reserved 011: 48 kHz 100: 88.2-96 kHz 101: Reserved 110: Reserved 111: 32kHz
1-0	FSSP	R/W	0

13.1.25 Register 37 (0x25)

Figure 117. Register 37 (0x25)

7	6	5	4	3	2	1	0
Reserved	IDFS	IDBK	IDSK	IDCH	IDCM	DCAS	IPLK
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 54. Register 37 (0x25) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6	IDFS	R/W	0	Ignore FS Detection – This bit controls whether to ignore the FS detection. When ignored, FS error will not cause a clock error. 0: Regard FS detection 1: Ignore FS detection
5	IDBK	R/W	0	Ignore SCLK Detection – This bit controls whether to ignore the SCLK detection against LRCLK. The SCLK must be stable between 32 FS and 256 FS inclusive or an error will be reported. When ignored, a SCLK error will not cause a clock error. 0: Regard SCLK detection 1: Ignore SCLK detection
4	IDSK	R/W	0	Ignore MCLK Detection – This bit controls whether to ignore the MCLK detection against LRCLK. Only some certain MCLK ratios within some error margin are allowed. When ignored, an MCLK error will not cause a clock error. 0: Regard MCLK detection 1: Ignore MCLK detection
3	IDCH	R/W	0	Ignore Clock Halt Detection – This bit controls whether to ignore the MCLK halt (static or frequency is lower than acceptable) detection. When ignored an MCLK halt will not cause a clock error. 0: Regard MCLK halt detection 1: Ignore MCLK halt detection
2	IDCM	R/W	0	Ignore LRCLK/SCLK Missing Detection – This bit controls whether to ignore the LRCLK/SCLK missing detection. The LRCLK/SCLK need to be in low state (not only static) to be deemed missing. When ignored an LRCLK/SCLK missing will not cause the DAC go into powerdown mode. 0: Regard LRCLK/SCLK missing detection 1: Ignore LRCLK/SCLK missing detection
1	DCAS	R/W	0	Disable Clock Divider Autoset – This bit enables or disables the clock auto set mode. When dealing with uncommon audio clock configuration, the auto set mode must be disabled and all clock dividers must be set manually. Addtionally, some clock detectors might also need to be disabled. The clock autoset feature will not work with PLL enabled in VCOM mode. In this case this feature has to be disabled and the clock dividers must be set manually. 0: Enable clock auto set 1: Disable clock auto set
0	IPLK	R/W	0	Ignore PLL Lock Detection – This bit controls whether to ignore the PLL lock detection. When ignored, PLL unlocks will not cause a clock error. The PLL lock flag at P0-R4, bit 4 is always correct regardless of this bit. 0: PLL unlocks raise clock error 1: PLL unlocks are ignored

13.1.26 Register 40 (0x28)

Figure 118. Register 40 (0x28)

7	6	5	4	3	2	1	0
Reserved		AFMT		Reserved		ALEN
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 55. Register 40 (0x28) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	–
5-4	AFMT	R/W	0	I2S Data Format – These bits control both input and output audio interface formats for DAC operation. 00: I2S 01: DSP 10: RTJ 11: LTJ
3-2	Reserved	R/W		Reserved
1	ALEN	R/W	1	I2S Word Length – These bits control both input and output audio interface sample word lengths for DAC operation. 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits
0	ALEN	R/W	0

13.1.27 Register 41 (0x29)

Figure 119. Register 41 (0x29)

7	6	5	4	3	2	1	0
AOFS
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 56. Register 41 (0x29) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	AOFS	R/W	0	I2S Shift – These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of SCLK from the starting (MSB) of audio frame to the starting of the desired audio sample. 00000000: offset = 0 SCLK (no offset) 00000001: ofsset = 1 SCLK 00000010: offset = 2 SCLKs … 11111111: offset = 256 SCLKs

13.1.28 Register 42 (0x2A)

Figure 120. Register 42 (0x2A)

7	6	5	4	3	2	1	0
Reserved		AUPL		Reserved		AUPR
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 57. Register 42 (0x2A) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W		Reserved
5	AUPL	R/W	0	Left DAC Data Path – These bits control the left channel audio data path connection. 00: Zero data (mute) 01: Left channel data 10: Right channel data 11: Reserved (do not set)
4		R/W	1
3-2	Reserved	R/W		Reserved
1	AUPR	R/W	0	Right DAC Data Path – These bits control the right channel audio data path connection. 00: Zero data (mute) 01: Right channel data 10: Left channel data 11: Reserved (do not set)
0		R/W	1

13.1.29 Register 43 (0x2B)

Figure 121. Register 43 (0x2B)

7	6	5	4	3	2	1	0
Reserved			PSEL
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 58. Register 43 (0x2B) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4-1	PSEL	R/W	0	DSP Program Selection – These bits select the DSP program to use for audio processing. 00000: Reserved 00001: Rom Mode 1 00010: Reserved 00011: Reserved
0		R/W	1

13.1.30 Register 44 (0x2C)

Figure 122. Register 44 (0x2C)

7	6	5	4	3	2	1	0
Reserved					CMDP
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 59. Register 44 (0x2C) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved			Reserved
2-0	CMDP	R/W	0	Clock Missing Detection Period – These bits set how long both SCLK and LRCLK keep low before the audio clocks deemed missing and the DAC transitions to powerdown mode. 000: about 1 second 001: about 2 seconds 010: about 3 seconds ... 111: about 8 seconds

13.1.31 Register 59 (0x3B)

Figure 123. Register 59 (0x3B)

7	6	5	4	3	2	1	0
Reserved	AMTL			Reserved	AMTR
R/W	R/W			R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 60. Register 59 (0x3B) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W		Reserved
6-4	AMTL	R/W	0	Auto Mute Time for Left Channel – These bits specify the length of consecutive zero samples at left channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec
3	Reserved	R/W		Reserved
2-0	AMTR	R/W	0	Auto Mute Time for Right Channel – These bits specify the length of consecutive zero samples at right channel before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec

13.1.32 Register 60 (0x3C)

Figure 124. Register 60 (0x3C)

7	6	5	4	3	2	1	0
Reserved						PCTL
R/W						R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 61. Register 60 (0x3C) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1-0	PCTL	R/W	0	Digital Volume Control – These bits control the behavior of the digital volume. 00: The volume for Left and right channels are independent 01: Right channel volume follows left channel setting

13.1.33 Register 61 (0x3D)

Figure 125. Register 61 (0x3D)

7	6	5	4	3	2	1	0
VOLL
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 62. Register 61 (0x3D) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VOLL	R/W	00110000	Left Digital Volume – These bits control the left channel digital volume. The digital volume is 24 dB to –103 dB in –0.5 dB step. 00000000: +24.0 dB 00000001: +23.5 dB … 00101111: +0.5 dB 00110000: 0.0 dB 00110001: –0.5 dB ... 11111110: –103 dB 11111111: Mute

13.1.34 Register 62 (0x3E)

Figure 126. Register 62 (0x3E)

7	6	5	4	3	2	1	0
VOLR
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 63. Register 62 (0x3E) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VOLR	R/W	00110000	Right Digital Volume – These bits control the right channel digital volume. The digital volume is 24 dB to –103 dB in –0.5 dB step. 00000000: +24.0 dB 00000001: +23.5 dB … 00101111: +0.5 dB 00110000: 0.0 dB 00110001: –0.5 dB ... 11111110: –103 dB 11111111: Mute

13.1.35 Register 63 (0x3F)

Figure 127. Register 63 (0x3F)

7	6	5	4	3	2	1	0
VNDF		VNDS		VNUF		VNUS
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 64. Register 63 (0x3F) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	VNDF	R/W	00	Digital Volume Normal Ramp Down Frequency – These bits control the frequency of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute request, asserted by XSMUTE pin or P0-R3. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	VNDS	R/W	11	Digital Volume Normal Ramp Down Step – These bits control the step of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute request, asserted by XSMUTE pin or P0-R3. 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-2	VNUF	R/W	00	Digital Volume Normal Ramp Up Frequency – These bits control the frequency of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request, asserted by XSMUTE pin or P0-R3. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly restore the volume (Instant unmute)
1-0	VNUS	R/W	11	Digital Volume Normal Ramp Up Step – These bits control the step of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request, asserted by XSMUTE pin or P0-R3. 00: Increment by 4 dB for each update 01: Increment by 2 dB for each update 10: Increment by 1 dB for each update 11: Increment by 0.5 dB for each update

13.1.36 Register 64 (0x40)

Figure 128. Register 64 (0x40)

7	6	5	4	3	2	1	0
VEDF		VEDS		Reserved
R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 65. Register 64 (0x40) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	VEDF	R/W	0	Digital Volume Emergency Ramp Down Frequency – These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	VEDS	R/W	1	Digital Volume Emergency Ramp Down Step – These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute. 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-0	Reserved	R/W		Reserved

13.1.37 Register 65 (0x41)

Figure 129. Register 65 (0x41)

7	6	5	4	3	2	1	0
Reserved					ACTL	AMLE	AMRE
R/W					R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 66. Register 65 (0x41) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W		Reserved
2	ACTL	R/W	1	Auto Mute ControlNOBUS – This bit controls the behavior of the auto mute upon zero sample detection. The time length for zero detection is set with P0-R59. 0: Auto mute left channel and right channel independently. 1: Auto mute left and right channels only when both channels are about to be auto muted.
1	AMLE	R/W	1	Auto Mute Left ChannelNOBUS – This bit enables or disables auto mute on right channel. Note that when right channel auto mute is disabled and the P0-R65, bit 2 is set to 1, the left channel will also never be auto muted. 0: Disable right channel auto mute 1: Enable right channel auto mute
0	AMRE	R/W	1	Auto Mute Right ChannelNOBUS – This bit enables or disables auto mute on left channel. Note that when left channel auto mute is disabled and the P0-R65, bit 2 is set to 1, the right channel will also never be auto muted. 0: Disable left channel auto mute 1: Enable left channel auto mute

13.1.38 Register 67 (0x43)

Figure 130. Register 67 (0x43)

7	6	5	4	3	2	1	0
DLPA		DRPA		DLPM		DRPM
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 67. Register 67 (0x43) Field Descriptions

Bit	Field	Type	Description
7-6	DLPA	R/W	Left DAC primary AC dither gain – These bits control the AC dither gain for left channel primary DAC modulator. 00: AC dither gain = 0.125 01: AC dither gain = 0.25
5-4	DRPA	R/W	Right DAC primary AC dither gain – These bits control the AC dither gain for right channel primary DAC modulator. 00: AC dither gain = 0.125 01: AC dither gain = 0.25
3-2	DLPM	R/W	Left DAC primary DEM dither gain – These bits control the dither gain for left channel primary Galton DEM. 00: DEM dither gain = 0.5 01: DEM dither gain = 1.0 Others: Reserved (do not set)
1-0	DRPM	R/W	Right DAC primary DEM dither gain – These bits control the dither gain for right channel primary Galton DEM. 00: DEM dither gain = 0.5 01: DEM dither gain = 1.0 Others: Reserved (do not set)

13.1.39 Register 68 (0x44)

Figure 131. Register 68 (0x44)

7	6	5	4	3	2	1	0
Reserved					DLPD
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 68. Register 68 (0x44) Field Descriptions

Bit	Field	Type	Reset	Description
7-3	Reserved	R/W		Reserved
2-0	DLPD	R/W	0	Left DAC primary DC dither – These bits control the DC dither amount to be added to the lower part of the left channel primary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^-11 × 1/32 FS 00000000010 : 2^-10 × 1/32 FS

13.1.40 Register 69 (0x45)

Figure 132. Register 69 (0x45)

7	6	5	4	3	2	1	0
DLPD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 69. Register 69 (0x45) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLPD	R/W	0	Left DAC primary DC dither – These bits control the DC dither amount to be added to the lower part of the left channel primary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^-11 × 1/32 FS 00000000010 : 2^-10 × 1/32 FS

13.1.41 Register 70 (0x46)

Figure 133. Register 70 (0x46)

7	6	5	4	3	2	1	0
DRPD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 70. Register 70 (0x46) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRPD	R/W	0	Right DAC primary DC dither – These bits control the DC dither amount to be added to the lower part of the right channel primary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^-11 × 1/32 FS 00000000010 : 2^-10 × 1/32 FS

13.1.42 Register 71 (0x47)

Figure 134. Register 71 (0x47)

7	6	5	4	3	2	1	0
DRPD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 71. Register 71 (0x47) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRPD	R/W	0	Right DAC primary DC dither – These bits control the DC dither amount to be added to the lower part of the right channel primary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^-11 × 1/32 FS 00000000010 : 2^-10 × 1/32 FS

13.1.43 Register 72 (0x48)

Figure 135. Register 72 (0x48)

7	6	5	4	3	2	1	0
DLSA		DRSA		DLSM		RSM
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 72. Register 72 (0x48) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DLSA	R/W	01	Left DAC secondary AC dither gain – These bits control the AC dither gain for left channel secondary DAC. 00: AC dither gain = 0.125 01: AC dither gain = 0.25
5-4	DRSA	R/W	01	Right DAC secondary AC dither gain – These bits control the AC dither gain for right channel secondary DAC modulator. 00: AC dither gain = 0.125 01: AC dither gain = 0.25 10: AC dither gain = 0.5 11: no AC dither
3-2	DLSM	R/W	01	Left DAC secondary DEM dither gain – These bits control the dither gain for left channel secondary Galton DEM. 00: DEM dither gain = 0.5 01: DEM dither gain = 1.0 Others: Reserved (do not set)
1-0	DRSM	R/W	01	Right DAC secondary DEM dither gain – These bits control the dither gain for right channel secondary Galton DEM. 00: DEM dither gain = 0.5 01: DEM dither gain = 1.0 Others: Reserved (do not set)

13.1.44 Register 73 (0x49)

Figure 136. Register 73 (0x49)

7	6	5	4	3	2	1	0
DLSD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 73. Register 73 (0x49) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLSD	R/W	0	Left DAC secondary DC dither – These bits control the DC dither amount to be added to the lower part of the left channel secondary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^–11 × 1/32 FS 00000000010 : 2^–10 × 1/32 FS

13.1.45 Register 74 (0x4A)

Figure 137. Register 74 (0x4A)

7	6	5	4	3	2	1	0
DLSD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 74. Register 74 (0x4A) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DLSD	R/W	0	Left DAC secondary DC dither – These bits control the DC dither amount to be added to the lower part of the left channel secondary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^–11 × 1/32 FS 00000000010 : 2^–10 × 1/32 FS

13.1.46 Register 75 (0x4B)

Figure 138. Register 75 (0x4B)

7	6	5	4	3	2	1	0
DRSD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 75. Register 75 (0x4B) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRSD	R/W	00000000	Right DAC secondary DC dither – These bits control the DC dither amount to be added to the lower part of the right channel secondary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^–11 × 1/32 FS 00000000010 : 2^–10 × 1/32 FS

13.1.47 Register 76 (0x4C)

Figure 139. Register 76 (0x4C)

7	6	5	4	3	2	1	0
DRSD
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 76. Register 76 (0x4C) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DRSD	R/W	00000000	Right DAC secondary DC dither – These bits control the DC dither amount to be added to the lower part of the right channel secondary DAC modulator. The DC dither is expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input. 00000000000 : No DC dither 00000000001 : 2^–11 × 1/32 FS 00000000010 : 2^–10 × 1/32 FS

13.1.48 Register 78 (0x4E)

Figure 140. Register 78 (0x4E)

7	6	5	4	3	2	1	0
OLOF
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 77. Register 78 (0x4E) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	OLOF	R/W	00000000	Left OFSCAL offset – These bits controls the amount of manual DC offset to be added to the left channel DAC output. The additional offset would be approximately the negative of the decimal value of this register divided by 4 in mV. 01111111 : –31.75 mV 01111110 : –31.50 mV … 00000010 : –0.50 mV 00000001 : –0.25 mV 00000000 : 0.0 mV 11111111 : +0.25 mV 11111110 : +0.50 mV … 10000000 : +32.0 mV

13.1.49 Register 79 (0x4F)

Figure 141. Register 79 (0x4F)

7	6	5	4	3	2	1	0
OROF
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 78. Register 79 (0x4F) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	OROF	R/W	0	Right OFSCAL offset – These bits controls the amount of manual DC offset to be added to the right channel DAC output. The additional offset would be approximately the negative of the decimal value of this register divided by 4 in mV. 01111111 : –31.75 mV 01111110 : –31.50 mV … 00000010 : –0.50 mV 00000001 : –0.25 mV 00000000 : 0.0 mV 11111111 : +0.25 mV 11111110 : +0.50 mV … 10000000 : +32.0 mV

13.1.50 Register 83 (0x53)

Figure 142. Register 83 (0x53)

7	6	5	4	3	2	1	0
Reserved			G0SL
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 79. Register 83 (0x53) Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W		Reserved
4-0	G0SL	R/W	0	GPIO0 Output Selection – These bits select the signal to output to GPIO0. To actually output the selected signal, the GPIO0 must be set to output mode at P0-R8. 0110: Clock invalid flag (clock error or clock changing or clock missing) 0111: Serial audio interface data output (SDOUT) 1000: Analog mute flag for left channel (low active) 1001: Analog mute flag for right channel (low active) 1010: PLL lock flag 1011: Charge pump clock 1100: Reserved 1101: Reserved 1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD 1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD INTERNAL 1100: Short detection flag for left channel 1101: Short detection flag for right channel 10000: PLL clock/4 10001: Oscillator clock/4 10010: Impedance sense flag for left channel 10011: Impedance sense flag for right channel 10100: Internal UVP flag, becomes low when VDD falls below roughly 2.7V 10101: Offset calibration flag, asserted when the system is offset calibrating itself. 10110: Clock error flag 10111: Clock changing flag 11000: Clock missing flag 11001: Clock halt detection flag 11010: DSP boot done flag 11011: Charge pump voltage output valid flag (low active) Others: N/A (zero)

13.1.51 Register 85 (0x55)

Figure 143. Register 85 (0x55)

7	6	5	4	3	2	1	0
Reserved			G2SL
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 80. Register 85 (0x55) Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4-0	G2SL	R/W	0	GPIO2 Output Selection – These bits select the signal to output to GPIO2. To actually output the selected signal, the GPIO2 must be set to output mode at P0-R8. 0000: off (low) 0001: DSP GPIO2 output 0010: Register GPIO2 output (P0-R86, bit 5) 0011: Auto mute flag (asserted when both L and R channels are auto muted) 0100: Auto mute flag for left channel 0101: Auto mute flag for right channel 0110: Clock invalid flag (clock error or clock changing or clock missing) 0111: Serial audio interface data output (SDOUT) 1000: Analog mute flag for left channel (low active) 1001: Analog mute flag for right channel (low active) 1010: PLL lock flag 1011: Charge pump clock 1100: Reserved 1101: Reserved 1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD 1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD INTERNAL 1100: Short detection flag for left channel 1101: Short detection flag for right channel 10000: PLL clock/4 10001: Oscillator clock/4 10010: Impedance sense flag for left channel 10011: Impedance sense flag for right channel 10100: Internal UVP flag, becomes low when VDD falls below roughly 2.7V 10101: Offset calibration flag, asserted when the system is offset calibrating itself. 10110: Clock error flag 10111: Clock changing flag 11000: Clock missing flag 11001: Clock halt detection flag 11010: DSP boot done flag 11011: Charge pump voltage output valid flag (low active) Others: N/A (zero)

13.1.52 Register 86 (0x56)

Figure 144. Register 86 (0x56)

7	6	5	4	3	2	1	0
R/W		R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 81. Register 86 (0x56) Register Field Descriptions

Bit	Field	Type	Description
7-6	Reserved	R/W	Reserved
5	GOUT2	R/W	GPIO Output Control – This bit controls the GPIO2 output when the selection at P0-R85 is set to 0010 (register output) 0: Output low 1: Output high
4	MUTE	R/W	This bit controls the MUTE output when the selection at P0-R84 is set to 0010 (register output). 0: Output low 1: Output high
3	GOUT0	R/W	This bit controls the GPIO0 output when the selection at P0-R83 is set to 0010 (register output) 0: Output low 1: Output high
2-0	Reserved	R/W	Reserved

13.1.53 Register 87 (0x57)

Figure 145. Register 87 (0x57)

7	6	5	4	3	2	1	0
R/W		R/W	R/W	R/W	R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 82. Register 87 (0x57) Field Descriptions

Bit	Field	Type	Description
7-6	Reserved	R/W	Reserved
5	GINV2	R/W	GPIO Output Inversion – This bit controls the polarity of GPIO2 output. When set to 1, the output will be inverted for any signal being selected. 0: Non-inverted 1: Inverted
4	MUTE	R/W	This bit controls the polarity of MUTE output. When set to 1, the output will be inverted for any signal being selected. 0: Non-inverted 1: Inverted
3	GINV0	R/W	This bit controls the polarity of GPIO0 output. When set to 1, the output will be inverted for any signal being selected. 0: Non-inverted 1: Inverted
2-0	Reserved	R/W	Reserved

13.1.54 Register 88 (0x58)

Figure 146. Register 88 (0x58)

7	6	5	4	3	2	1	0
DIEI
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 83. Register 88 (0x58) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIEI	RO	0x84	Die ID, Device ID = 0x84

13.1.55 Register 91 (0x5B)

Figure 147. Register 91 (0x5B)

7	6	5	4	3	2	1	0
Reserved	DTFS			DTSR
R/W	R			R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 84. Register 91 (0x5B) Field Descriptions

Bit	Field	Type	Description
7	Reserved	R/W	Reserved
6-4	DTFS	R	Detected FS – These bits indicate the currently detected audio sampling rate. 000: Error (Out of valid range) 001: 8 kHz 010: 16 kHz 011: 32-48 kHz 100: 88.2-96 kHz 101: 176.4-192 kHz 110: 384 kHz
3-0	DTSR	R	Detected MCLK Ratio – These bits indicate the currently detected MCLK ratio. Note that even if the MCLK ratio is not indicated as error, clock error might still be flagged due to incompatible combination with the sampling rate. Specifically the MCLK ratio must be high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The absolute MCLK frequency must also be lower than 50 MHz. 0000: Ratio error (The MCLK ratio is not allowed) 0001: MCLK = 32 FS 0010: MCLK = 48 FS 0011: MCLK = 64 FS 0100: MCLK = 128 FS 0101: MCLK = 192 FS 0110: MCLK = 256 FS 0111: MCLK = 384 FS 1000: MCLK = 512 FS 1001: MCLK = 768 FS 1010: MCLK = 1024 FS 1011: MCLK = 1152 FS 1100: MCLK = 1536 FS 1101: MCLK = 2048 FS 1110: MCLK = 3072 FS

13.1.56 Register 92 (0x5C)

Figure 148. Register 92 (0x5C)

7	6	5	4	3	2	1	0
Reserved							DTBR
R/W							R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 85. Register 92 (0x5C) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	DTBR	R	0	Detected SCLK Ratio (MSB)

13.1.57 Register 93 (0x5D)

Figure 149. Register 93 (0x5D)

7	6	5	4	3	2	1	0
DTBR
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 86. Register 93 (0x5D) Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DTBR	R/W		Detected SCLK Ratio (LSB) – These bits indicate the currently detected SCLK ratio, i.e. the number of SCLK clocks in one audio frame. Note that for extreme case of SCLK = 1 FS (which is not usable anyway), the detected ratio will be unreliable

13.1.58 Register 94 (0x5E)

Figure 150. Register 94 (0x5E)

7	6	5	4	3	2	1	0
Reserved	CDST6	CDST5	CDST4	CDST3	CDST2	CDST1	CDST0
R/W	R	R	R	R	R	R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 87. Register 94 (0x5E) Field Descriptions

Bit	Field	Type	Reset	Description
7	Reserved	R/W	0	Reserved
6	CDST6	R		Clock Detector Status – This bit indicates whether the MCLK clock is present or not. 0: MCLK is present 1: MCLK is missing (halted)
5	CDST5	R		This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled. 0: PLL is locked 1: PLL is unlocked
4	CDST4	R		This bit indicates whether the both LRCLK and SCLK are missing (tied low) or not. 0: LRCLK and/or SCLK is present 1: LRCLK and SCLK are missing
3	CDST3	R		This bit indicates whether the combination of current sampling rate and MCLK ratio is valid for clock auto set. 0: The combination of FS/MCLK ratio is valid 1: Error (clock auto set is not possible)
2	CDST2	R		This bit indicates whether the MCLK is valid or not. The MCLK ratio must be detectable to be valid. There is a limitation with this flag, that is, when the low period of LRCLK is less than or equal to five SCLKs, this flag will be asserted (MCLK invalid reported). 0: MCLK is valid 1: MCLK is invalid
1	CDST1	R		This bit indicates whether the SCLK is valid or not. The SCLK ratio must be stable and in the range of 32-256FS to be valid. 0: SCLK is valid 1: SCLK is invalid
0	CDST0	R		This bit indicated whether the audio sampling rate is valid or not. The sampling rate must be detectable to be valid. There is a limitation with this flag, that is when this flag is asserted and P0-R37 is set to ignore all asserted error flags such that the DAC recovers, this flag will be de-asserted (sampling rate invalid not reported anymore). 0: Sampling rate is valid 1: Sampling rate is invalid

13.1.59 Register 95 (0x5F)

Figure 151. Register 95 (0x5F)

7	6	5	4	3	2	1	0
Reserved			LTSH	Reserved	CKMF	CSRF	CERF
R/W			R	R/W	R	R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 88. Register 95 (0x5F) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	LTSH	R		Latched Clock Halt – This bit indicates whether MCLK halt has occurred. The bit is cleared when read. 0: MCLK halt has not occurred 1: MCLK halt has occurred since last read
3	Reserved	R/W	0	Reserved
2	CKMF	R		Clock Missing – This bit indicates whether the LRCLK and SCLK are missing (tied low). 0: LRCLK and/or SCLK is present 1: LRCLK and SCLK are missing
1	CSRF	R		Clock Resync Request – This bit indicates whether the clock resynchronization is in progress. 0: Not resynchronizing 1: Clock resynchronization is in progress
0	CERF	R		Clock Error – This bit indicates whether a clock error has occurred. The bit is cleared when read 0: Clock error has not occurred 1: Clock error has occurred.

13.1.60 Register 108 (0x6C)

Figure 152. Register 108 (0x6C)

7	6	5	4	3	2	1	0
Reserved						AMLM	AMRM
R/W						R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 89. Register 108 (0x6C) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1	AMLM	R		Left Analog Mute Monitor – This bit is a monitor for left channel analog mute status. 0: Mute 1: Unmute
0	AMRM	R		Right Analog Mute Monitor – This bit is a monitor for right channel analog mute status. 0: Mute 1: Unmute

13.1.61 Register 119 (0x77)

Figure 153. Register 119 (0x77)

7	6	5	4	3	2	1	0
Reserved		GPIN2	MUTE	GPIN0	Reserved	Reserved	Reserved
R/W		R	R	R	R	R	R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 90. Register 119 (0x77) Field Descriptions

Bit	Field	Type	Reset	Description
7-6	Reserved	R/W	0	Reserved
5	GPIN2	RO		GPIO Input States – This bit indicates the logic level at GPIO2 pin. 0: Low 1: High
4	MUTE	RO		This bit indicates the logic level at MUTE pin. 0: Low 1: High
3	GPIN0	RO		This bit indicates the logic level at GPIO0 pin. 0: Low 1: High
2		RO		N/A 0: Low 1: High
1		RO		N/A 0: Low 1: High
0		RO		N/A 0: Low 1: High

13.1.62 Register 120 (0x78)

Figure 154. Register 120 (0x78)

7	6	5	4	3	2	1	0
Reserved			AMFL	Reserved			AMFR
R/W			R	R/W			R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 91. Register 120 (0x78) Field Descriptions

Bit	Field	Type	Reset	Description
7-5	Reserved	R/W	0	Reserved
4	AMFL	R		Auto Mute Flag for Left Channel – This bit indicates the auto mute status for left channel. 0: Not auto muted 1: Auto muted
3-1	Reserved	R/W	0	Reserved
0	AMFR	R		Auto Mute Flag for Right Channel – This bit indicates the auto mute status for right channel. 0: Not auto muted 1: Auto muted

13.2 Registers - Page 1

13.2.1 Register 1 (0x01)

Figure 155. Register 1 (0x01)

7	6	5	4	3	2	1	0
Reserved							OSEL
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 92. Register 1 (0x01) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	OSEL	R/W	0	Output Amplitude Type - This bit selects the output amplitude type. The clock autoset feature will not work with PLL enabled in VCOM mode. In this case this feature has to be disabled via P0-R37 and the clock dividers must be set manually. 0: VREF mode (Constant output amplitude against AVDD variation) 1: VCOM mode (Output amplitude is proportional to AVDD variation)

13.2.2 Register 2 (0x02)

Figure 156. Register 2 (0x02)

7	6	5	4	3	2	1	0
Reserved			LAGN	Reserved			RAGN
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 93. Register 2 (0x02) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	LAGN	R/W	Analog Gain Control for Left Channel - This bit controls the left channel analog gain. 0: 0 dB 1: -6 dB
3-1	Reserved	R/W	Reserved
0	RAGN	R/W	Analog Gain Control for Right Channel - This bit controls the right channel analog gain. 0: 0 dB 1: -6 dB

13.2.3 Register 6 (0x06)

Figure 157. Register 6 (0x06)

7	6	5	4	3	2	1	0
Reserved							AMCT
R/W							R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 94. Register 6 (0x06) Field Descriptions

Bit	Field	Type	Reset	Description
7-1	Reserved	R/W	0	Reserved
0	AMCT	R/W	1	Analog Mute Control -This bit enables or disables analog mute following digital mute. 0: Disabled 1: Enabled

13.2.4 Register 7 (0x07)

Figure 158. Register 7 (0x07)

7	6	5	4	3	2	1	0
Reserved			AGBL	Reserved			AGBR
R/W			R/W	R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 95. Register 7 (0x07) Field Descriptions

Bit	Field	Type	Description
7-5	Reserved	R/W	Reserved
4	AGBL	R/W	Analog +10% Gain for Left Channel - This bit enables or disables amplitude boost mode for left channel. 0: Normal amplitude 1: +10% (+0.8 dB) boosted amplitude
3-1	Reserved	R/W	Reserved
0	AGBR	R/W	Analog +10% Gain for Right Channel - This bit enables or disables amplitude boost mode for right channel. 0: Normal amplitude 1: +10% (+0.8 dB) boosted amplitude

13.2.5 Register 9 (0x09)

Figure 159. Register 9 (0x09)

7	6	5	4	3	2	1	0
Reserved						DEME	VCPD
R/W						R/W	R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 96. Register 9 (0x09) Field Descriptions

Bit	Field	Type	Reset	Description
7-2	Reserved	R/W	0	Reserved
1	DEME	R/W	0	VCOM Pin as De-emphasis Control - This bit controls whether to use the DEEMP/VCOM pin as De-emphasis control. 0: Disabled (DEEMP/VCOM is not used to control De-emphasis) 1: Enabled (DEEMP/VCOM is used to control De-emphasis)
0	VCPD	R/W	1	Power down control for VCOM - This bit controls VCOM powerdown switch. 0: VCOM is powered on 1: VCOM is powered down

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13 Register Maps

13.1 Registers - Page 0

13.1.1 Register 1 (0x01)

Table 27. Register 1 (0x01) Field Descriptions

Table 28. Register 2 (0x02) Field Descriptions

Table 29. Register 3 (0x03) Field Descriptions

Table 30. Register 4 (0x04) Field Descriptions

13.1.2 Register 6 (0x06)

Table 31. Register 6 (0x06) Field Descriptions

13.1.3 Register 7 (0x07)

Table 32. Register 7 (0x07) Field Descriptions

13.1.4 Register 8 (0x08)

Table 33. Register 8 (0x08) Field Descriptions

13.1.5 Register 9 (0x09)

Table 34. Register 9 (0x09) Field Descriptions

13.1.6 Register 12 (0x0C)

Table 35. Register 12 (0x0C) Field Descriptions

13.1.7 Register 13 (0x0D)

Table 36. Register 13 (0x0D) Field Descriptions

13.1.8 Register 14 (0x0E)

Table 37. Register 14 (0x0E) Field Descriptions

13.1.9 Register 15 (0x0F)

Table 38. Register 15 (0x0F) Field Descriptions

13.1.10 Register 16 (0x10)

Table 39. Register 16 (0x10) Field Descriptions

13.1.11 Register 17 (0x11)

Table 40. Register 17 (0x11) Field Descriptions

13.1.12 Register 18 (0x12)

Table 41. Register 18 (0x12) Field Descriptions

13.1.13 Register 20 (0x14)

Table 42. Register 20 (0x14) Field Descriptions

13.1.14 Register 21 (0x15)

Table 43. Register 21 (0x15) Field Descriptions

13.1.15 Register 22 (0x16)

Table 44. Register 22 (0x16) Field Descriptions

13.1.16 Register 23 (0x17)

Table 45. Register 23 (0x17) Field Descriptions

13.1.17 Register 24 (0x18)

Table 46. Register 24 (0x18) Field Descriptions

13.1.18 Register 27 (0x1B)

Table 47. Register 27 (0x1B) Field Descriptions

13.1.19 Register 28 (0x1C)

Table 48. Register 28 (0x1C) Field Descriptions

13.1.20 Register 29 (0x1D)

Table 49. Register 29 (0x1D) Field Descriptions

13.1.21 Register 30 (0x1E)

Table 50. Register 30 (0x1E) Field Descriptions

13.1.22 Register 32 (0x20)

Table 51. Register 32 (0x20) Field Descriptions

13.1.23 Register 33 (0x21)

Table 52. Register 33 (0x21) Field Descriptions

13.1.24 Register 34 (0x22)

Table 53. Register 34 (0x22) Field Descriptions

13.1.25 Register 37 (0x25)

Table 54. Register 37 (0x25) Field Descriptions

13.1.26 Register 40 (0x28)

Table 55. Register 40 (0x28) Field Descriptions

13.1.27 Register 41 (0x29)

Table 56. Register 41 (0x29) Field Descriptions

13.1.28 Register 42 (0x2A)

Table 57. Register 42 (0x2A) Field Descriptions

13.1.29 Register 43 (0x2B)

Table 58. Register 43 (0x2B) Field Descriptions

13.1.30 Register 44 (0x2C)

Table 59. Register 44 (0x2C) Field Descriptions

13.1.31 Register 59 (0x3B)

Table 60. Register 59 (0x3B) Field Descriptions

13.1.32 Register 60 (0x3C)

Table 61. Register 60 (0x3C) Field Descriptions

13.1.33 Register 61 (0x3D)

Table 62. Register 61 (0x3D) Field Descriptions

13.1.34 Register 62 (0x3E)

Table 63. Register 62 (0x3E) Field Descriptions

13.1.35 Register 63 (0x3F)

Table 64. Register 63 (0x3F) Field Descriptions

13.1.36 Register 64 (0x40)