JAJSHH6 May   2019 TAS5806M

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
      1. 8.7.1 Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode
      2. 8.7.2 Bridge Tied Load (BTL) Configuration Curves
      3. 8.7.3 Parallel Bridge Tied Load (PBTL) Configuration
  9. 9 Parametric Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Power Supplies
      2. 10.3.2 Device Clocking
      3. 10.3.3 Serial Audio Port – Clock Rates
      4. 10.3.4 Clock Halt Auto-recovery
      5. 10.3.5 Sample Rate on the Fly Change
      6. 10.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 10.3.7 Digital Audio Processing
      8. 10.3.8 Class D Audio Amplifier
        1. 10.3.8.1 Speaker Amplifier Gain Select
    4. 10.4 Device Functional Modes
      1. 10.4.1 Software Control
      2. 10.4.2 Speaker Amplifier Operating Modes
        1. 10.4.2.1 BTL Mode
        2. 10.4.2.2 PBTL Mode
      3. 10.4.3 Low EMI Modes
        1. 10.4.3.1 Minimize EMI with Spread Spectrum
        2. 10.4.3.2 Channel to Channel Phase shift
        3. 10.4.3.3 Multi-Devices PWM Phase Synchronization
      4. 10.4.4 Thermal Foldback
      5. 10.4.5 Device State Control
      6. 10.4.6 Device Modulation
        1. 10.4.6.1 BD Modulation
        2. 10.4.6.2 1SPW Modulation
        3. 10.4.6.3 Hybrid Modulation
    5. 10.5 Programming and Control
      1. 10.5.1 I2 C Serial Communication Bus
      2. 10.5.2 Slave Address
        1. 10.5.2.1 Random Write
        2. 10.5.2.2 Sequential Write
        3. 10.5.2.3 Random Read
        4. 10.5.2.4 Sequential Read
        5. 10.5.2.5 DSP Memory Book, Page and BQ update
        6. 10.5.2.6 Example Use
        7. 10.5.2.7 Checksum
          1. 10.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 10.5.2.7.2 Exclusive or (XOR) Checksum
      3. 10.5.3 Control via Software
        1. 10.5.3.1 Startup Procedures
        2. 10.5.3.2 Shutdown Procedures
        3. 10.5.3.3 Protection and Monitoring
          1. 10.5.3.3.1 Over-current Shutdown (OCSD)
          2. 10.5.3.3.2 DC Detect
    6. 10.6 Register Maps
      1. 10.6.1 CONTROL PORT Registers
        1. 10.6.1.1  RESET_CTRL Register (Offset = 1h) [reset = 0x00]
          1. Table 7. RESET_CTRL Register Field Descriptions
        2. 10.6.1.2  DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
          1. Table 8. DEVICE_CTRL_1 Register Field Descriptions
        3. 10.6.1.3  DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]
          1. Table 9. DEVICE_CTRL_2 Register Field Descriptions
        4. 10.6.1.4  I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
          1. Table 10. I2C_PAGE_AUTO_INC Register Field Descriptions
        5. 10.6.1.5  SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
          1. Table 11. SIG_CH_CTRL Register Field Descriptions
        6. 10.6.1.6  CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
          1. Table 12. CLOCK_DET_CTRL Register Field Descriptions
        7. 10.6.1.7  SDOUT_SEL Register (Offset = 30h) [reset = 0h]
          1. Table 13. SDOUT_SEL Register Field Descriptions
        8. 10.6.1.8  I2S_CTRL Register (Offset = 31h) [reset = 0x00]
          1. Table 14. I2S_CTRL Register Field Descriptions
        9. 10.6.1.9  SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
          1. Table 15. SAP_CTRL1 Register Field Descriptions
        10. 10.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
          1. Table 16. SAP_CTRL2 Register Field Descriptions
        11. 10.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
          1. Table 17. SAP_CTRL3 Register Field Descriptions
        12. 10.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
          1. Table 18. FS_MON Register Field Descriptions
        13. 10.6.1.13 BCK_MON Register (Offset = 38h) [reset = 0x00]
          1. Table 19. BCK_MON Register Field Descriptions
        14. 10.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
          1. Table 20. CLKDET_STATUS Register Field Descriptions
        15. 10.6.1.15 CHANNEL_FORCE_HIZ Register (Offset = 40h) [reset = 0x01]
          1. Table 21. CHANNEL_FORCE_HIZ Register Field Descriptions
        16. 10.6.1.16 DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]
          1. Table 22. DIG_VOL_CTR Register Field Descriptions
        17. 10.6.1.17 DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]
          1. Table 23. DIG_VOL_CTRL2 Register Field Descriptions
        18. 10.6.1.18 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
          1. Table 24. DIG_VOL_CTRL3 Register Field Descriptions
        19. 10.6.1.19 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
          1. Table 25. AUTO_MUTE_CTRL Register Field Descriptions
        20. 10.6.1.20 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
          1. Table 26. AUTO_MUTE_TIME Register Field Descriptions
        21. 10.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0x00]
          1. Table 27. ANA_CTRL Register Field Descriptions
        22. 10.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]
          1. Table 28. AGAIN Register Field Descriptions
        23. 10.6.1.23 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
          1. Table 29. BQ_WR_CTRL1 Register Field Descriptions
        24. 10.6.1.24 DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
          1. Table 30. DAC_CTRL Register Field Descriptions
        25. 10.6.1.25 ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]
          1. Table 31. ADR_PIN_CTRL Register Field Descriptions
        26. 10.6.1.26 ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]
          1. Table 32. ADR_PIN_CONFIG Register Field Descriptions
        27. 10.6.1.27 DSP_MISC Register (Offset = 66h) [reset = 0h]
          1. Table 33. DSP_MISC Register Field Descriptions
        28. 10.6.1.28 DIE_ID Register (Offset = 67h) [reset = 0h]
          1. Table 34. DIE_ID Register Field Descriptions
        29. 10.6.1.29 POWER_STATE Register (Offset = 68h) [reset = 0x00]
          1. Table 35. POWER_STATE Register Field Descriptions
        30. 10.6.1.30 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
          1. Table 36. AUTOMUTE_STATE Register Field Descriptions
        31. 10.6.1.31 PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]
          1. Table 37. PHASE_CTR Register Field Descriptions
        32. 10.6.1.32 SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
          1. Table 38. SS_CTRL0 Register Field Descriptions
        33. 10.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
          1. Table 39. SS_CTRL1 Register Field Descriptions
        34. 10.6.1.34 SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]
          1. Table 40. SS_CTRL2 Register Field Descriptions
        35. 10.6.1.35 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
          1. Table 41. SS_CTRL3 Register Field Descriptions
        36. 10.6.1.36 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
          1. Table 42. SS_CTRL4 Register Field Descriptions
        37. 10.6.1.37 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
          1. Table 43. CHAN_FAULT Register Field Descriptions
        38. 10.6.1.38 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
          1. Table 44. GLOBAL_FAULT1 Register Field Descriptions
        39. 10.6.1.39 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
          1. Table 45. GLOBAL_FAULT2 Register Field Descriptions
        40. 10.6.1.40 OT WARNING Register (Offset = 73h) [reset = 0x00]
          1. Table 46. OT_WARNING Register Field Descriptions
        41. 10.6.1.41 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
          1. Table 47. PIN_CONTROL1 Register Field Descriptions
        42. 10.6.1.42 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
          1. Table 48. PIN_CONTROL2 Register Field Descriptions
        43. 10.6.1.43 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
          1. Table 49. MISC_CONTROL Register Field Descriptions
        44. 10.6.1.44 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
          1. Table 50. FAULT_CLEAR Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Bootstrap Capacitors
      2. 11.1.2 Inductor Selections
      3. 11.1.3 Power Supply Decoupling
      4. 11.1.4 Output EMI Filtering
    2. 11.2 Typical Applications
      1. 11.2.1 2.0 (Stereo BTL) System
      2. 11.2.2 Design Requirements
      3. 11.2.3 Detailed Design Procedure
        1. 11.2.3.1 Step1:Hardware Integration
        2. 11.2.3.2 Step2: Speaker Tuning
        3. 11.2.3.3 Software Integration
        4. 11.2.3.4 Application Curves
      4. 11.2.4 Mono (PBTL) system
      5. 11.2.5 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 DVDD Supply
    2. 12.2 PVDD Supply
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 General Guidelines for Audio Amplifiers
      2. 13.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 13.1.3 Optimizing Thermal Performance
        1. 13.1.3.1 Device, Copper, and Component Layout
        2. 13.1.3.2 Stencil Pattern
          1. 13.1.3.2.1 PCB footprint and Via Arrangement
          2. 13.1.3.2.2 Solder Stencil
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.6.1 CONTROL PORT Registers

Table 5 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in Table 5 should be considered as reserved locations and the register contents should not be modified.

Table 5. CONTROL PORT Registers

Offset Acronym Register Name Section
1h RESET_CTRL Register 1 Go
2h DEVICE_CTRL_1 Register 2 Go
3h DEVICE_CTRL_2 Register 3 Go
Fh I2C_PAGE_AUTO_INC Register 15 Go
28h SIG_CH_CTRL Register 40 Go
29h CLOCK_DET_CTRL Register 41 Go
30h SDOUT_SEL Register 48 Go
31h I2S_CTRL Register 49 Go
33h SAP_CTRL1 Register 51 Go
34h SAP_CTRL2 Register 52 Go
35h SAP_CTRL3 Register 53 Go
37h FS_MON Register 55 Go
38h BCK_MON Register 56 Go
39h CLKDET_STATUS Register 57 Go
40h CHANNEL_FORCE_HIZ Register 58 Go
4Ch DIG_VOL_CTRL Register 76 Go
4Eh DIG_VOL_CTRL2 Register 78 Go
4Fh DIG_VOL_CTRL3 Register 79 Go
50h AUTO_MUTE_CTRL Register 80 Go
51h AUTO_MUTE_TIME Register 81 Go
53h ANA_CTRL Register 83 Go
54h AGAIN Register 84 Go
5Ch BQ_WR_CTRL1 Register 92 Go
5Dh DAC_CTRL Register 93 Go
60h ADR_PIN_CTRL Register 96 Go
61h ADR_PIN_CONFIG Register 97 Go
66h DSP_MISC Register 102 Go
67h DIE_ID Register 103 Go
68h POWER_STATE Register 104 Go
69h AUTOMUTE_STATE Register 105 Go
6Ah PHASE_CTRL Register 106 Go
6Bh SS_CTRL0 Register 107 Go
6Ch SS_CTRL1 Register 108 Go
6Dh SS_CTRL2 Register 109 Go
6Eh SS_CTRL3 Register 110 Go
6Fh SS_CTRL4 Register 111 Go
70h CHAN_FAULT Register 112 Go
71h GLOBAL_FAULT1 Register 113 Go
72h GLOBAL_FAULT2 Register 114 Go
73h OT WARNING Register 115 Go
74h PIN_CONTROL1 Register 116 Go
75h PIN_CONTROL2 Register 117 Go
76h MISC_CONTROL Register 118 Go
78h FAULT_CLEAR Register 120 Go

Complex bit access types are encoded to fit into small table cells. Table 6 shows the codes that are used for access types in this section.

Table 6. CONTROL PORT Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value