JAJSHH5 May 2019 TAS5806MD
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Serial Audio Port Timing | |||||
fSCLK | SCLK frequency | 1.024 | MHz | ||
tSCLK | SCLK period | 40 | ns | ||
tSCLKL | SCLK pulse width, low | 16 | ns | ||
tSCLKH | SCLK pulse width, high | 16 | ns | ||
tSL | SCLK rising to LRCK/FS edge | 8 | ns | ||
tLS | LRCK/FS Edge to SCLK rising edge | 8 | ns | ||
tSU | Data setup time, before SCLK rising edge | 8 | ns | ||
tDH | Data hold time, after SCLK rising edge | 8 | ns | ||
tDFS | Data delay time from SCLK falling edge | 15 | ns | ||
I2C Bus Timing – Standard | |||||
fSCL | SCL clock frequency | 100 | kHz | ||
tBUF | Bus free time between a STOP and START condition | 4.7 | µs | ||
tLOW | Low period of the SCL clock | 4.7 | µs | ||
tHI | High period of the SCL clock | 4 | µs | ||
tRS-SU | Setup time for (repeated) START condition | 4.7 | µs | ||
tS-HD | Hold time for (repeated) START condition | 4 | µs | ||
tD-SU | Data setup time | 250 | ns | ||
tD-HD | Data hold time | 0 | 900 | ns | |
tSCL-R | Rise time of SCL signal | 20 + 0.1CB | 1000 | ns | |
tSCL-R1 | Rise time of SCL signal after a repeated START condition and after an acknowledge bit | 20 + 0.1CB | 1000 | ns | |
tSCL-F | Fall time of SCL signal | 20 + 0.1CB | 1000 | ns | |
tSDA-R | Rise time of SDA signal | 20 + 0.1CB | 1000 | ns | |
tSDA-F | Fall time of SDA signal | 20 + 0.1CB | 1000 | ns | |
tP-SU | Setup time for STOP condition | 4 | µs | ||
I2C Bus Timing –
Fast |
|||||
fSCL | SCL clock frequency | 400 | kHz | ||
tBUF | Bus free time between a STOP and START condition | 1.3 | µs | ||
tLOW | Low period of the SCL clock | 1.3 | µs | ||
tHI | High period of the SCL clock | 600 | ns | ||
tRS-SU | Setup time for (repeated)START condition | 600 | ns | ||
tRS-HD | Hold time for (repeated)START condition | 600 | ns | ||
tD-SU | Data setup time | 100 | ns | ||
tD-HD | Data hold time | 0 | 900 | ns | |
tSCL-R | Rise time of SCL signal | 20 + 0.1CB | 300 | ns | |
tSCL-R1 | Rise time of SCL signal after a repeated START condition and after an acknowledge bit | 20 + 0.1CB | 300 | ns | |
tSCL-F | Fall time of SCL signal | 20 + 0.1CB | 300 | ns | |
tSDA-R | Rise time of SDA signal | 20 + 0.1CB | 300 | ns | |
tSDA-F | Fall time of SDA signal | 20 + 0.1CB | 300 | ns | |
tP-SU | Setup time for STOP condition | 600 | ns | ||
tSP | Pulse width of spike suppressed | 50 | ns |