JAJSHH5
May 2019
TAS5806MD
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
4
改訂履歴
5
概要(続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
8.7.1
Bridge Tied Load (BTL) Configuration Curves with 1 SPW Mode
8.7.2
Bridge Tied Load (BTL) Configuration Curves
8.7.3
Parallel Bridge Tied Load (PBTL) Configuration
8.7.4
Headphone Driver
8.7.5
Line Driver
9
Parametric Measurement Information
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Power Supplies
10.3.2
Device Clocking
10.3.3
Serial Audio Port – Clock Rates
10.3.4
Clock Halt Auto-recovery
10.3.5
Sample Rate on the Fly Change
10.3.6
Serial Audio Port - Data Formats and Bit Depths
10.3.7
Digital Audio Processing
10.3.8
Class D Audio Amplifier
10.3.8.1
Speaker Amplifier Gain Select
10.4
Device Functional Modes
10.4.1
Software Control
10.4.2
Speaker Amplifier Operating Modes
10.4.2.1
BTL Mode
10.4.2.2
PBTL Mode
10.4.3
Low EMI Modes
10.4.3.1
Minimize EMI with Spread Spectrum
10.4.3.2
Channel to Channel Phase shift
10.4.3.3
Multi-Devices PWM Phase Synchronization
10.4.4
Thermal Foldback
10.4.5
Headphone Control
10.4.6
Device State Control
10.4.7
Device Modulation
10.4.7.1
BD Modulation
10.4.7.2
1SPW Modulation
10.4.7.3
Hybrid Modulation
10.5
Programming and Control
10.5.1
I2 C Serial Communication Bus
10.5.2
Slave Address
10.5.2.1
Random Write
10.5.2.2
Sequential Write
10.5.2.3
Random Read
10.5.2.4
Sequential Read
10.5.2.5
DSP Memory Book, Page and BQ update
10.5.2.6
Example Use
10.5.2.7
Checksum
10.5.2.7.1
Cyclic Redundancy Check (CRC) Checksum
10.5.2.7.2
Exclusive or (XOR) Checksum
10.5.3
Control via Software
10.5.3.1
Startup Procedures
10.5.3.2
Shutdown Procedures
10.5.3.3
Protection and Monitoring
10.5.3.3.1
Overcurrent Shutdown (OCSD)
10.5.3.3.2
DC Detect
10.6
Register Maps
10.6.1
CONTROL PORT Registers
10.6.1.1
RESET_CTRL Register (Offset = 1h) [reset = 0x00]
Table 7.
RESET_CTRL Register Field Descriptions
10.6.1.2
DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
Table 8.
DEVICE_CTRL_1 Register Field Descriptions
10.6.1.3
DEVICE_CTRL_2 Register (Offset = 3h) [reset = 0x10]
Table 9.
DEVICE_CTRL_2 Register Field Descriptions
10.6.1.4
I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
Table 10.
I2C_PAGE_AUTO_INC Register Field Descriptions
10.6.1.5
SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
Table 11.
SIG_CH_CTRL Register Field Descriptions
10.6.1.6
CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
Table 12.
CLOCK_DET_CTRL Register Field Descriptions
10.6.1.7
SDOUT_SEL Register (Offset = 30h) [reset = 0h]
Table 13.
SDOUT_SEL Register Field Descriptions
10.6.1.8
I2S_CTRL Register (Offset = 31h) [reset = 0x00]
Table 14.
I2S_CTRL Register Field Descriptions
10.6.1.9
SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
Table 15.
SAP_CTRL1 Register Field Descriptions
10.6.1.10
SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
Table 16.
SAP_CTRL2 Register Field Descriptions
10.6.1.11
SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
Table 17.
SAP_CTRL3 Register Field Descriptions
10.6.1.12
FS_MON Register (Offset = 37h) [reset = 0x00]
Table 18.
FS_MON Register Field Descriptions
10.6.1.13
BCK_MON Register (Offset = 38h) [reset = 0x00]
Table 19.
BCK_MON Register Field Descriptions
10.6.1.14
CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
Table 20.
CLKDET_STATUS Register Field Descriptions
10.6.1.15
CHANNEL_FORCE_HIZ Register (Offset = 40h) [reset = 0x01]
Table 21.
CHANNEL_FORCE_HIZ Register Field Descriptions
10.6.1.16
DIG_VOL_CTL Register (Offset = 4Ch) [reset = 30h]
Table 22.
DIG_VOL_CTR Register Field Descriptions
10.6.1.17
DIG_VOL_CTRL2 Register (Offset = 4Eh) [reset = 0x33]
Table 23.
DIG_VOL_CTRL2 Register Field Descriptions
10.6.1.18
DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
Table 24.
DIG_VOL_CTRL3 Register Field Descriptions
10.6.1.19
AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
Table 25.
AUTO_MUTE_CTRL Register Field Descriptions
10.6.1.20
AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
Table 26.
AUTO_MUTE_TIME Register Field Descriptions
10.6.1.21
ANA_CTRL Register (Offset = 53h) [reset = 0x00]
Table 27.
ANA_CTRL Register Field Descriptions
10.6.1.22
AGAIN Register (Offset = 54h) [reset = 0x00]
Table 28.
AGAIN Register Field Descriptions
10.6.1.23
BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x00]
Table 29.
BQ_WR_CTRL1 Register Field Descriptions
10.6.1.24
DAC_CTRL Register (Offset = 5Dh) [reset = 0xF8]
Table 30.
DAC_CTRL Register Field Descriptions
10.6.1.25
ADR_PIN_CTRL Register (Offset = 60h) [reset = 0h]
Table 31.
ADR_PIN_CTRL Register Field Descriptions
10.6.1.26
ADR_PIN_CONFIG Register (Offset = 61h) [reset = 0x00]
Table 32.
ADR_PIN_CONFIG Register Field Descriptions
10.6.1.27
DSP_MISC Register (Offset = 66h) [reset = 0h]
Table 33.
DSP_MISC Register Field Descriptions
10.6.1.28
DIE_ID Register (Offset = 67h) [reset = 0h]
Table 34.
DIE_ID Register Field Descriptions
10.6.1.29
POWER_STATE Register (Offset = 68h) [reset = 0x00]
Table 35.
POWER_STATE Register Field Descriptions
10.6.1.30
AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
Table 36.
AUTOMUTE_STATE Register Field Descriptions
10.6.1.31
PHASE_CTRL Register (Offset = 6Ah) [reset = 0x00]
Table 37.
PHASE_CTR Register Field Descriptions
10.6.1.32
SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
Table 38.
SS_CTRL0 Register Field Descriptions
10.6.1.33
SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
Table 39.
SS_CTRL1 Register Field Descriptions
10.6.1.34
SS_CTRL2 Register (Offset = 6Dh) [reset = 0x50]
Table 40.
SS_CTRL2 Register Field Descriptions
10.6.1.35
SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
Table 41.
SS_CTRL3 Register Field Descriptions
10.6.1.36
SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
Table 42.
SS_CTRL4 Register Field Descriptions
10.6.1.37
CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
Table 43.
CHAN_FAULT Register Field Descriptions
10.6.1.38
GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
Table 44.
GLOBAL_FAULT1 Register Field Descriptions
10.6.1.39
GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
Table 45.
GLOBAL_FAULT2 Register Field Descriptions
10.6.1.40
OT WARNING Register (Offset = 73h) [reset = 0x00]
Table 46.
OT_WARNING Register Field Descriptions
10.6.1.41
PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
Table 47.
PIN_CONTROL1 Register Field Descriptions
10.6.1.42
PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
Table 48.
PIN_CONTROL2 Register Field Descriptions
10.6.1.43
MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
Table 49.
MISC_CONTROL Register Field Descriptions
10.6.1.44
HP_CONTROL Register (Offset = 77h) [reset = 0x00]
Table 50.
HP_CONTROL Register Field Descriptions
10.6.1.45
FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
Table 51.
FAULT_CLEAR Register Field Descriptions
11
Application and Implementation
11.1
Application Information
11.1.1
Bootstrap Capacitors
11.1.2
Inductor Selections
11.1.3
Power Supply Decoupling
11.1.4
Output EMI Filtering
11.2
Typical Applications
11.2.1
2.0 (Stereo BTL) System
11.2.2
Design Requirements
11.2.3
Detailed Design Procedure
11.2.3.1
Step 1: Hardware Integration
11.2.3.2
Step2: Speaker Tuning
11.2.3.3
Software Integration
11.2.4
Application Curves
11.2.5
Mono (PBTL) system
11.2.6
Application Curves
12
Power Supply Recommendations
12.1
DVDD Supply
12.2
PVDD Supply
13
Layout
13.1
Layout Guidelines
13.1.1
General Guidelines for Audio Amplifiers
13.1.2
Importance of PVDD Bypass Capacitor Placement on PVDD Network
13.1.3
Optimizing Thermal Performance
13.1.3.1
Device, Copper, and Component Layout
13.1.3.2
Stencil Pattern
13.1.3.2.1
PCB footprint and Via Arrangement
13.1.3.2.2
Solder Stencil
13.2
Layout Example
14
デバイスおよびドキュメントのサポート
14.1
デバイス・サポート
14.1.1
デバイスの項目表記
14.1.2
開発サポート
14.2
ドキュメントの更新通知を受け取る方法
14.3
コミュニティ・リソース
14.4
商標
14.5
静電気放電に関する注意事項
14.6
Glossary
15
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DCP|38
MPDS520B
サーマルパッド・メカニカル・データ
DCP|38
PPTD170A
発注情報
jajshh5_oa
jajshh5_pm
10.4
Device Functional Modes