JAJSHH5 May 2019 TAS5806MD
PRODUCTION DATA.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BST_A- | 1 | P | Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A- |
OUT_A- | 2 | AO | Negative pin for differential speaker amplifier output A- |
PGND | 3, 36 | G | Ground reference for power device circuitry. Connect this pin to system ground. |
BST_A+ | 4 | P | Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+ |
OUT_A+ | 5 | AO | Positive pin for differential speaker amplifier output A+ |
PVDD | 6, 7, 32, 33 | P | PVDD voltage input |
DGND | 8, 12 | G | Digital ground |
DVDD | 9 | P | 3.3-V or 1.8-V digital power supply |
ADR/FAULT | 10 | DIO | Different I2 C device address can be set by selecting different pull up resistor to DVDD, see Table 3 for details. After power up, ADR/FAULT can be redefine as FAULT, go to Page0, Book0, set register 0x61 = 0x0b first, then set register 0x60 = 0x01 |
VR_DIG | 11 | P | Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices |
LRCLK | 13 | DI | Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary. |
SCLK | 14 | DI | Bit clock for the digital signal that is active on the input data line of the serial data port. |
SDIN | 15 | DI | Data line to the serial data port |
HP_GND | 16 | G | Headphone Ground |
HPVDD | 17 | P | Headphone Positive Power Supply |
HPR_IN | 18 | AI | Headphone In Right |
HPL_IN | 19 | AI | Headphone In Left |
HPR_OUT | 20 | AO | Headphone Out Right |
HPL_OUT | 21 | AO | Headphone Out Left |
HPVSS | 22 | P | Headphone Negative Power Supply (Generated Internally) |
CPN | 23 | Negative connection point for charge pump fly cap | |
NC | 24 | No Connect Pin. Can be shorted to PVCC or shorted to GND or left open. | |
CPP | 25 | Positive connection point for charge pump fly cap | |
SDOUT | 26 | DO | Serial Audio data output, the source data can select as Pre-DSP or Post DSP, by setting the register 0x30h. |
SDA | 27 | DI/O | I2C serial control data interface input/output |
SCL | 28 | DI | I2C serial control clock input |
PDN | 29 | DI | Power Down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators. Low, Power Down Device; High, Enable Device. |
AVDD | 30 | P | Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices |
AGND | 31 | G | Analog ground |
OUT_B+ | 34 | AO | Positive pin for differential speaker amplifier output B+ |
BST_B+ | 35 | P | Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+ |
OUT_B- | 37 | AO | Negative pin for differential speaker amplifier output B |
BST_B- | 38 | P | Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B- |
PowerPAD™ | P | Connect to the system Ground |