JAJSKP7 December   2020 TAS5822M

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
      2. 6.7.2 Parallel Bridge Tied Load (PBTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
    8. 6.8 Parametric Measurement Information
      1. 6.8.1 Power Consumption Summary
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Clock Halt Auto-recovery
      5. 7.3.5 Sample Rate on the Fly Change
      6. 7.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Minimize EMI with Spread Spectrum
      4. 7.4.4 Minimize EMI with channel to channel phase shift
      5. 7.4.5 Minimize EMI with Multi-Devices PWM Phase Synchronization
      6. 7.4.6 Thermal Foldback
      7. 7.4.7 Device State Control
      8. 7.4.8 Device Modulation
        1. 7.4.8.1 BD Modulation
        2. 7.4.8.2 1SPW Modulation
        3. 7.4.8.3 Hybrid Modulation
    5. 7.5 Programming and Control
      1. 7.5.1 I2 C Serial Communication Bus
      2. 7.5.2 Slave Address
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
        5. 7.5.2.5 DSP Memory Book, Page and BQ update
        6. 7.5.2.6 Example Use
        7. 7.5.2.7 Checksum
          1. 7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.2.7.2 Exclusive or (XOR) Checksum
      3. 7.5.3 Control via Software
        1. 7.5.3.1 Startup Procedures
        2. 7.5.3.2 Shutdown Procedures
        3. 7.5.3.3 Protection and Monitoring
          1. 7.5.3.3.1 Over current Shutdown (OCSD)
          2. 7.5.3.3.2 Speaker DC Protection
          3. 7.5.3.3.3 Device Over Temperature Protection
          4. 7.5.3.3.4 Over Voltage Protection
          5. 7.5.3.3.5 Under Voltage Protection
          6. 7.5.3.3.6 Clock Fault
    6. 7.6 Register Maps
      1. 7.6.1 CONTROL PORT Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 2.0 (Stereo BTL) System
      2. 8.2.2 MONO （PBTL) System
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Bootstrap Capacitors
          2. 8.2.2.2.2 Inductor Selections
          3. 8.2.2.2.3 Power Supply Decoupling
          4. 8.2.2.2.4 Output EMI Filtering
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 DVDD Supply
    2. 9.2 PVDD Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines for Audio Amplifiers
      2. 10.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 10.1.3 Optimizing Thermal Performance
        1. 10.1.3.1 Device, Copper, and Component Layout
        2. 10.1.3.2 Stencil Pattern
          1. 10.1.3.2.1 PCB footprint and Via Arrangement
          2. 10.1.3.2.2 Solder Stencil
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 サポート・リソース
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Free-air room temperature 25°C, 1SPW Mode, LC filter=4.7uH+0.68uF, Fsw=768kHz, Class D Bandwidth=175kHz, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital I/O
|IIH| Input logic high current level
for DVDD referenced digital
input pins		 VIN(DigIn) = VDVDD 10 uA
|IIL| Input logic low current level
for DVDD referenced digital
input pins		 VIN(DigIn) = 0 V –10 uA
VIH(Digin) Input logic high threshold for
DVDD referenced digital
inputs		 70% VDVDD
VIL(Digin) Input logic low threshold for
DVDD referenced digital
inputs		 30% VDVDD
VOH(Digin) Output logic high voltage
level		 IOH = 4 mA 80% VDVDD
VOL(Digin) Output logic low voltage level IOH = –4 mA 20% VDVDD
I2C CONTROL PORT
CL(I2C) Allowable load capacitance
for each I2C Line		 400 pF
fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz
fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz
SERIAL AUDIO PORT
tDLY Required LRCLK/FS to SCLK
rising edge delay		 5 ns
DSCLK Allowable SCLK duty cycle 40% 60%
fS Supported input sample rates 32 96 kHz
fSCLK Supported SCLK frequencies 32 64 fS
fSCLK SCLK frequency 24.576 MHz
AMPLIFIER OPERATING MODE AND DC PRAMETERS
toff Turn-off Time Excluding volume ramp 10 ms
AV(SPK_AMP) Programmable Gain Value represents the "peak voltage" disregarding
clipping due to lower PVDD
Measured at 0 dB input(1FS)		 13.75 29.4 dBV
ΔAV(SPK_AMP) Amplifier gain error Gain = 29.4dBV 0.5 dB
fSPK_AMP Switching frequency of the
speaker amplifier		 384 kHz
480 kHz
576 kHz
768 kHz
1024 kHz
RDS(on) Drain-to-source on resistance
of the individual output
MOSFETs		 FET + Metallization. VPVDD=24V, I(OUT)=500mA,
TJ=25℃		 90 mΩ
PROTECTION
OCETHRES Over-Current Error Threshold Speaker Output Current (Post LC filter), Speaker
current		 6 7 A
UVETHRES(PVDD) PVDD under voltage error
threshold		 3.7 4 4.2 V
OVETHRES(PVDD) PVDD over voltage error
threshold		 27 28.1 29.2 V
DCETHRES Output DC Error protection
threshold		 Class D Amplifier's output DC voltage cross
speaker load to trigger Output DC Fault protection		 1.9 V
TDCDET Output DC Detect time Class D Amplifier's output remain at or above DCETHRES 570 ms
OTETHRES Over temperature error
threshold		 160 ℃
OTEHystersis Over temperature error
hysteresis		 10 ℃
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit3 135 °C
OL Open Load Detection Open Load Detection for ChA or ChB or both 40 70 Ω
SL Short Load Detection Short Load Detection for ChA or ChB or both 2 Ω
AUDIO PERFORMACNE (STEREO BTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data,
programmable gain configured with 29.4dBV
analog gain, VPVDD =
18 V, 1SPW Modulation		 –6.5 6.5 mV
PO(SPK) Output Power (Per Channel) VPVDD = 13.5 V, RSPK = 6 Ω, f = 1 KHz, THD+N =10% 15 W
VPVDD = 13.5 V, RSPK = 6 Ω, f = 1 KHz, THD+N =1% 13 W
VPVDD = 18 V, RSPK = 6 Ω, f = 1 KHz, THD+N =10% 27 W
VPVDD = 18 V, RSPK = 6 Ω, f = 1 KHz, THD+N =1% 23 W
VPVDD = 24 V, RSPK = 8 Ω, f = 1 KHz, THD+N =1% 35 W
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz, RSPK =
6 Ω)		 VPVDD = 13.5 V 0.03 %
VPVDD = 18 V 0.02 %
VPVDD = 24 V 0.02 %
ICN(SPK) Idle channel noise(Aweighted,
AES17)		 VPVDD = 13.5 V, LC-filter, Load=6 Ω 35 µVrms
VPVDD = 18 V, LC-filter ,Load=6 Ω 35 µVrms
DR Dynamic range A-Weighted, -60 dBFS method. VPVDD = 24 V,
Analog Gain = 29.4dBV		 111 dB
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=24V		 111 dB
A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=13.5V		 106 dB
PSRR Power supply rejection ratio Injected Noise = 1 KHz, 1 Vrms, VPVDD = 13.5 V,
input audio signal = digital zero		 72 dB
X-talkSPK Cross-talk (worst case
between left-to-right and
right-to-left coupling)		 f = 1 KHz, based on Inductor (DFEG7030D-4R7)
from Murata		 100 dB
AUDIO PERFORMANCE (MONO PBTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data,
programmable gain configured with 29.4dBV
Analog gain, VPVDD = 18 V, 1SPW Modulation		 –6.5 6.5 mV
PO(SPK) Output Power VPVDD = 24 V, RSPK = 4 Ω, f = 1KHz, THD+N =1% 65 W
VPVDD = 18 V, RSPK = 3 Ω, f = 1KHz, THD+N =1% 45 W
VPVDD = 18 V, RSPK = 3 Ω, f = 1KHz, THD+N =10% 55 W
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz)		 VPVDD = 18 V, LC-filter, RSPK = 3 Ω 0.05 %
VPVDD = 24 V, LC-filter, RSPK = 4 Ω 0.02 %
DR Dynamic range A-Weighted, -60 dBFS method, VPVDD=24V, RSPK= 3 Ω. 111 dB
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=18V, RSPK = 3 Ω		 108 dB
A-Weighted,referenced to 1% THD+N Output
Level, VPVDD=13.5V, RSPK = 2 Ω		 106 dB
PSRR Power supply rejection ratio Injected Noise = 1 KHz, 1 Vrms,VPVDD = 18 V,
input audio signal = digital zero		 72 dB