JAJSSI1 December   2023 TAS5827

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 5.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Supplies
      2. 6.3.2 Device Clocking
      3. 6.3.3 Serial Audio Port – Clock Rates
      4. 6.3.4 Clock Halt Auto-recovery
      5. 6.3.5 Sample Rate on the Fly Change
      6. 6.3.6 Serial Audio Port - Data Formats and Bit Depths
    4. 6.4 Device Functional Modes
      1. 6.4.1 Software Control
      2. 6.4.2 Speaker Amplifier Operating Modes
        1. 6.4.2.1 BTL Mode
        2. 6.4.2.2 PBTL Mode
      3. 6.4.3 Low EMI Modes
        1. 6.4.3.1 Spread Spectrum
        2. 6.4.3.2 Channel to Channel Phase Shift
        3. 6.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 6.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 6.4.3.3.2 Phase Synchronization With GPIO
      4. 6.4.4 Thermal Foldback
      5. 6.4.5 Device State Control
      6. 6.4.6 Device Modulation
        1. 6.4.6.1 BD Modulation
        2. 6.4.6.2 1SPW Modulation
        3. 6.4.6.3 Hybrid Modulation
      7. 6.4.7 Programming and Control
        1. 6.4.7.1 I2C Serial Communication Bus
        2. 6.4.7.2 Hardware Control Mode
        3. 6.4.7.3 I2C Target Address
          1. 6.4.7.3.1 Random Write
          2. 6.4.7.3.2 Sequential Write
          3. 6.4.7.3.3 Random Read
          4. 6.4.7.3.4 Sequential Read
          5. 6.4.7.3.5 DSP Memory Book, Page and BQ update
          6. 6.4.7.3.6 Checksum
            1. 6.4.7.3.6.1 Cyclic Redundancy Check (CRC) Checksum
            2. 6.4.7.3.6.2 Exclusive or (XOR) Checksum
        4. 6.4.7.4 Control via Software
          1. 6.4.7.4.1 Startup Procedures
          2. 6.4.7.4.2 Shutdown Procedures
        5. 6.4.7.5 Protection and Monitoring
          1. 6.4.7.5.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 6.4.7.5.2 Overcurrent Shutdown (OCSD)
          3. 6.4.7.5.3 DC Detect Error
          4. 6.4.7.5.4 Overtemperature Shutdown (OTSD)
          5. 6.4.7.5.5 PVDD Overvoltage and Undervoltage Error
          6. 6.4.7.5.6 PVDD Drop Detection
          7. 6.4.7.5.7 Clock Fault
    5. 6.5 Register Maps
      1. 6.5.1 reg_map Registers
  8. 7 Application and Implementation
    1. 7.1 Typical Applications
      1. 7.1.1 2.0 (Stereo BTL) System
      2. 7.1.2 Mono (PBTL) Systems
      3. 7.1.3 Layout Guidelines
        1. 7.1.3.1 General Guidelines for Audio Amplifiers
        2. 7.1.3.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 7.1.3.3 Optimizing Thermal Performance
          1. 7.1.3.3.1 Device, Copper, and Component Layout
          2. 7.1.3.3.2 Stencil Pattern
          3. 7.1.3.3.3 PCB footprint and Via Arrangement
          4. 7.1.3.3.4 Solder Stencil
        4. 7.1.3.4 Layout Example
  9. 8 Power Supply Recommendations
    1. 8.1 DVDD Supply
    2. 8.2 PVDD Supply
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation

Free-air room temperature 25°C (unless otherwise noted). Measurements were made using Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 384 kHz, 80 kHz Class D Amplifier Loop Bandwidth, the LC filter used was 10 μH / 0.68 μF （Post-Filter PBTL, the merging of the two output channels after the inductor portion of the output filter, see connect method in Section 7.1.2）, unless otherwise noted.

GUID-20231201-SS0I-D0V8-D3JS-J1ZZ52WD0NLS-low.svg
Figure 5-56 THD+N vs Frequency-PBTL
GUID-20231201-SS0I-ZCRM-FRWB-BHTRVVSFBGFX-low.svg
Figure 5-58 THD+N vs Frequency-PBTL
GUID-20231201-SS0I-7C49-FSV4-240NQVXSMSM6-low.svg
Figure 5-57 THD+N vs Frequency-PBTL
GUID-20231201-SS0I-LXPC-J8ZL-WLMNMV1V0VPG-low.svg
Figure 5-59 THD+N vs Frequency-PBTL
GUID-20231201-SS0I-6DCC-DLS8-M63CTXQBHZ4B-low.svg
Figure 5-60 THD+N vs Frequency-PBTL
GUID-20231201-SS0I-D23J-WQH7-D5LD6GLFTPWQ-low.svg
Figure 5-62 THD+N vs Output Power-PBTL
GUID-20231201-SS0I-99XV-ZK90-GT86CTDVGCT5-low.svg
Figure 5-64 THD+N vs Output Power-PBTL
GUID-20231201-SS0I-CLM9-BNVD-TWS0NR7WBZNW-low.svg
Figure 5-66 Output Power vs Supply Voltage
GUID-20231201-SS0I-VZSR-FNVG-LXTXLMCBDNJJ-low.svg
2 Ω Load 
Figure 5-68 Idle Channel Noise vs Supply Voltage
GUID-20231201-SS0I-K54Z-ZGKS-NCCVXRQQHBH9-low.svg
Figure 5-70 Efficiency vs Output Power
GUID-20231201-SS0I-QZCN-NJGJ-DMMPJ2HMTH9W-low.svg
Figure 5-72 Efficiency vs Output Power
GUID-20231201-SS0I-NRHT-QZQT-H0HDX7JJJ05R-low.svg
Figure 5-61 THD+N vs Frequency-PBTL
GUID-20231201-SS0I-TDN2-LK4Z-5XC8DHGGCBPN-low.svg
Figure 5-63 THD+N vs Output Power-PBTL
GUID-20231201-SS0I-QWNX-7QMQ-P9WXV74SQSMK-low.svg
Figure 5-65 Output Power vs Supply Voltage
GUID-20231201-SS0I-MHZZ-RV7J-BCDQDFDGKS2T-low.svgFigure 5-67 Output Power vs Supply Voltage
GUID-20231201-SS0I-PTBS-3PJN-TK639N2VNJQ3-low.svg
4 Ω Load
Figure 5-69 Idle Channel Noise vs Supply Voltage
GUID-20231201-SS0I-BSFP-X4MS-L9FJFRCP7C2P-low.svg
Figure 5-71 Efficiency vs Output Power