TA = 25 °C, VVDD
= 3.3 V, VBAT = PVDD = 14.4 V, RL = 2 Ω, fIN = 1 kHz,
fs = 48 kHz, fSW = 2.1 MHz, Output
Configuration: PBTL, AES17 filter, default I2C settings, LC
filter: 3.3 μH - DFEG7030D-3R3M. See Figure 10-3 (unless otherwise noted)
Figure 7-28 THD+N
vs Power - PBTL - 14.4V![THD+N
vs Frequency - PBTL - 14.4 V GUID-20210601-CA0I-MQZQ-MNQC-JMGDC0LRVB4W-low.gif](/ods/images/JAJSM70A/GUID-20210601-CA0I-MQZQ-MNQC-JMGDC0LRVB4W-low.gif)
PVDD = 14.4 V |
PO = 1 W |
PBTL |
Figure 7-30 THD+N
vs Frequency - PBTL - 14.4 V
Figure 7-32 Output Power vs Supply Voltage - PBTL
Figure 7-34 Efficiency vs Output power - PBTL - 2 Ω (Zoomed)Figure 7-36 Noise
vs Supply Voltage - PBTL
Figure 7-29 THD+N
vs Power - PBTL - 24 V![THD+N
vs Frequency - PBTL - 24 V GUID-20210601-CA0I-2CBP-SXC4-GNCSHGGFWZRG-low.gif](/ods/images/JAJSM70A/GUID-20210601-CA0I-2CBP-SXC4-GNCSHGGFWZRG-low.gif)
PVDD = 24 V |
PO = 1 W |
PBTL |
Figure 7-31 THD+N
vs Frequency - PBTL - 24 V
Figure 7-33 Efficiency vs Output Power - PBTL - 2 Ω
Figure 7-35 Power
Dissipation vs Output Power - PBTL - 2 Ω