11.2.1.3.1 Hardware Design

Use the following procedure for the hardware design:

• Determine the input format. The input format can be either I²S or TDM mode. The mode determines the correct pin connections and the I²C register settings.
• Determine the power output that is required into the load. The power requirement determines the required power-supply voltage and current. The output reconstruction-filter components that are required are also driven by the output power.
• With the requirements, adjust the typical application schematic in Figure 59 for the input connections.

11.2.1.3.2 Digital Input and the Serial Audio Port

The TAS6424L-Q1 device supports four different digital input formats which are: I²S, Right Justified, Left Justified, and TDM mode. Depending on the format, the device can support 16, 18, 20, 24, and 32 bit data. The supported frequencies are 96 kHz, 48 kHz, and 44.1 kHz. Please see Table 13 for the I²C register, SAP Control, for the complete matrix to set up the serial audio port.

11.2.1.3.3 Bootstrap Capacitors

The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must be sized appropriately for the system specification. A special condition can occur where the bootstrap may sag if the capacitor is not sized accordingly. The special condition is just below clipping where the PWM is slightly less than 100% duty cycle with sustained low-frequency signals. Changing the bootstrap capacitor value to 2.2 µF for driving subwoofers that require frequencies below 30 Hz may be necessary.

11.2.1.3.4 Output Reconstruction Filter

The output FETs drive the amplifier outputs in an H-Bridge configuration. These transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. The amplifier outputs require a reconstruction filter that comprises a series inductor and a capacitor to ground on each output, generally called an LC filter. The LC filter attenuates the PWM frequency and reduces electromagnetic emissions, allowing the reconstructed audio signal to pass to the speakers. refer to the Class-D LC Filter Design, (SLOA119) for a detailed description of proper component description and design of the LC filter based upon the specified load and frequency response. The recommended low-pass cutoff frequency of the LC filter is dependent on the selected switching frequency. The low-pass cutoff frequency can be as high as 100 kHz for a PWM frequency of 2.1 MHz. At a PWM frequency of 384 kHz the low-pass cutoff frequency should be less than 40 kHz. Certain specifications must be understood for a proper inductor. The inductance value is given at zero current, but the TAS6424L-Q1 device will have current. Use the inductance versus current curve for the inductor to make sure the inductance does not drop below 2 µH (for f_SW = 2.1 MHz) at the maximum current provided by the system design. The DCR of the inductor directly affects the output power of the system design. The lower the DCR, the more power is provided to the speakers. The typical inductor DCR for a 4 Ω system is 40 to 50 mΩ and for a 2 Ω system is 20 to 25 mΩ.

11.2.2.1.1 Detailed Design Procedure

As a starting point, refer to the Detailed Design Procedure section for the BTL application. PBTL mode requires schematic changes in the output stage as shown in Figure 62. The other required changes include setting up the I²C registers correctly (see Table 13) and selecting which frame or channel to use on each output. Bit 6 in register 0x21 controls the frame selection.