JAJSPM4A September   2016  – February 2023 TCA6408A-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Translation
      2. 8.3.2 I/O Port
      3. 8.3.3 Interrupt Output ( INT)
      4. 8.3.4 Reset Input ( RESET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Bus Transactions
        1. 8.5.2.1 Writes
        2. 8.5.2.2 Reads
    6. 8.6 Register Map
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 9.2.1.2 Minimizing ICC When I/O is Used to Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-On Reset Requirements
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 商標
    3. 10.3 静電気放電に関する注意事項
    4. 10.4 用語集
  11. 11サポート・リソース
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

I2C Interface

The TCA6408A-Q1 has a standard bidirectional I2C interface that is controlled by a controller device in order to be configured or read the status of this device. Each target on the I2C bus has a specific device address to differentiate between other target devices that are on the same I2C bus. Many target devices require configuration upon startup to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read.

The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I2C lines. (For further details, see the application report, I2C Pull-up Resistor Calculation (SLVA689)). Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. See Figure 8-3 and Figure 8-4.

The following is the general procedure for a controller to access a target device:

  1. If a controller wants to send data to a target:
    • Controller-transmitter sends a START condition and addresses the target-receiver.
    • Controller-transmitter sends data to target-receiver.
    • Controller-transmitter terminates the transfer with a STOP condition.
  2. If a controller wants to receive or read data from a target:
    • Controller-receiver sends a START condition and addresses the target-transmitter.
    • Controller-receiver sends the requested register to read to target-transmitter.
    • Controller-receiver receives data from the target-transmitter.
    • Controller-receiver terminates the transfer with a STOP condition.
GUID-0D9F5F59-616C-4460-9564-9ACB37B9EE08-low.gifFigure 8-3 Definition of Start and Stop Conditions
GUID-08EECCC9-9D3B-4239-AC22-2832C6EBC0FA-low.gifFigure 8-4 Bit Transfer

Table 8-2 shows the interface definition for the TCA6408A-Q1 device.

Table 8-2 Interface Definition
BYTEBIT
7 (MSB)6543210 (LSB)
I2C target addressLHLLLLADDRR/ W
I/O data busP7P6P5P4P3P2P1P0