JAJSPM4A September   2016  – February 2023 TCA6408A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Translation
      2. 8.3.2 I/O Port
      3. 8.3.3 Interrupt Output ( INT)
      4. 8.3.4 Reset Input ( RESET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Bus Transactions
        1. 8.5.2.1 Writes
        2. 8.5.2.2 Reads
    6. 8.6 Register Map
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 9.2.1.2 Minimizing ICC When I/O is Used to Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-On Reset Requirements
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 商標
    3. 10.3 静電気放電に関する注意事項
    4. 10.4 用語集
  11. 11サポート・リソース
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.2.1 Writes

To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as well as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the controller then sends the register address of the register to which it wishes to write. The target will acknowledge again, letting the controller know it is ready. After this, the controller starts sending the register data to the target until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller terminates the transmission with a STOP condition.

Figure 8-5 and Figure 8-6 show an example of writing a single byte to a target register.

GUID-68342220-4C0C-4312-879F-4C48312EF70F-low.svgFigure 8-5 Write to Register

GUID-73573674-C369-4AD6-9E29-41B1BFE35495-low.svgFigure 8-6 Write to the Polarity Inversion Register