JAJSPM3D July 2010 – January 2023 TCA6424A
PRODUCTION DATA
Following the successful acknowledgment of the address byte, the bus controller sends a command byte, which is stored in the control register in the TCA6424A. Four bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversion, or configuration) that will be affected. The control register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
The control register includes an Auto-Increment (AI) bit which is the most significant bit (bit 7) of the command byte. At power-up, the control register defaults to 00 (hex), with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.
If AI is 1, the 2 least significant bits are automatically incremented after a read or write. This allows the user to program and/or read the 3 register banks sequentially. If more than 3 bytes of data are written when AI is 1, previous data in the selected registers will be overwritten. Reserved registers are skipped and not accessed (refer to Table 5).
If AI is 0, the 2 least significant bits are not incremented after data is read or written. During a read operation, the same register bank is read each time. During a write operation, data is written to the same register bank each time.
Reserved command codes and command byte outside the range stated in the Command Byte table must not be accessed for proper device functionality.
CONTROL REGISTER BITS | AUTO-INCREMENT STATE | COMMAND BYTE (HEX) | REGISTER | PROTOCOL | POWER-UP DEFAULT | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
AI | B6 | B5 | B4 | B3 | B2 | B1 | B0 | |||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Disable | 00 | Input Port 0 | Read byte | xxxx xxxx(1) |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Enable | 80 | |||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Disable | 01 | Input Port 1 | Read byte | xxxx xxxx(1) |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Enable | 81 | |||
0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Disable | 02 | Input Port 2 | Read byte | xxxx xxxx(1) |
1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Enable | 82 | |||
0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Disable | 03 | Reserved | Reserved | Reserved |
1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Enable | 83 | |||
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Disable | 04 | Output Port 0 | Read/write byte | 1111 1111 |
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Enable | 84 | |||
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | Disable | 05 | Output Port 1 | Read/write byte | 1111 1111 |
1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | Enable | 85 | |||
0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | Disable | 06 | Output Port 2 | Read/write byte | 1111 1111 |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | Enable | 86 | |||
0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | Disable | 07 | Reserved | Reserved | Reserved |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | Enable | 87 | |||
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Disable | 08 | Polarity Inversion Port 0 | Read/write byte | 0000 0000 |
1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Enable | 88 | |||
0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Disable | 09 | Polarity Inversion Port 1 | Read/write byte | 0000 0000 |
1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Enable | 89 | |||
0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | Disable | 0A | Polarity Inversion Port 2 | Read/write byte | 0000 0000 |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | Enable | 8A | |||
0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | Disable | 0B | Reserved | Reserved | Reserved |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | Enable | 8B | |||
0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Disable | 0C | Configuration Port 0 | Read/write byte | 1111 1111 |
1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Enable | 8C | |||
0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Disable | 0D | Configuration Port 1 | Read/write byte | 1111 1111 |
1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Enable | 8D | |||
0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Disable | 0E | Configuration Port 2 | Read/write byte | 1111 1111 |
1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Enable | 8E | |||
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Disable | 0F | Reserved | Reserved | Reserved |
1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Enable | 8F |