The TCA9534A is a 16-pin device that provides 8 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I2C bus (or SMBus) protocol. The device can operate with a power supply voltage ranging from 1.65 V to 5.5 V, which allows for use with a wide range of devices. The device supports both 100-kHz (Standard-mode) and 400-kHz (Fast-mode) clock frequencies. I/O expanders such as the TCA9534A provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and other similar devices.
The features of the TCA9534A include an interrupt that is generated on the INT pin. This allows the master to know when an input port changes state. The A0, A1, and A2 hardware selectable address pins allow up to eight TCA9534A devices on the same I2C bus. The device can also be reset to its default sate by cycling the power supply and causing a power-on reset.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TCA9534A | TSSOP (16) | 5.00 mm × 4.40 mm |
SOIC (16) | 10.30 mm × 7.50 mm |
Changes from B Revision (December 2016) to C Revision
Changes from A Revision (September 2014) to B Revision
Changes from * Revision (August 2014) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | A0 | I | Address input. Connect directly to VCC or ground |
2 | A1 | I | Address input. Connect directly to VCC or ground |
3 | A2 | I | Address input. Connect directly to VCC or ground |
4 | P0 | I/O | P-port input-output. Push-pull design structure. At power on, P0 is configured as an input |
5 | P1 | I/O | P-port input-output. Push-pull design structure. At power on, P1 is configured as an input |
6 | P2 | I/O | P-port input-output. Push-pull design structure. At power on, P2 is configured as an input |
7 | P3 | I/O | P-port input-output. Push-pull design structure. At power on, P3 is configured as an input |
8 | GND | — | Ground |
9 | P4 | I/O | P-port input-output. Push-pull design structure. At power on, P4 is configured as an input |
10 | P5 | I/O | P-port input-output. Push-pull design structure. At power on, P5 is configured as an input |
11 | P6 | I/O | P-port input-output. Push-pull design structure. At power on, P6 is configured as an input |
12 | P7 | I/O | P-port input-output. Push-pull design structure. At power on, P7 is configured as an input |
13 | INT | O | Interrupt output. Connect to VCC through a pull-up resistor |
14 | SCL | I | Serial clock bus. Connect to VCC through a pull-up resistor |
15 | SDA | I/O | Serial data bus. Connect to VCC through a pull-up resistor |
16 | VCC | — | Supply voltage |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.5 | 6 | V | |
VI | Input voltage (2) | –0.5 | 6 | V | |
VO | Output voltage (2) | –0.5 | 6 | V | |
IIK | Input clamp current | VI < 0 | –20 | mA | |
IOK | Output clamp current | VO < 0 | –20 | mA | |
IIOK | Input-output clamp current | VO < 0 or VO > VCC | ±20 | mA | |
IOL | Continuous output low current through a single P-port | VO = 0 to VCC | 50 | mA | |
IOH | Continuous output high current through a single P-port | VO = 0 to VCC | –50 | mA | |
ICC | Continuous current through GND by all P-ports, INT, and SDA | 250 | mA | ||
Continuous current through VCC by all P-ports | –160 | ||||
TJ(MAX) | Maximum junction temperature | 100 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1000 |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC | Supply voltage | 1.65 | 5.5 | V | ||
VIH | High-level input voltage | SCL, SDA | VCC = 1.65 V to 5.5 V | 0.7 × VCC | VCC(1) | V |
A0, A1, A2, P7–P0 | VCC = 1.65 V to 2.7 V | 0.7 × VCC | 5.5 | |||
VIL | Low-level input voltage | SCL, SDA | VCC = 1.65 V to 5.5 V | –0.5 | 0.3 × VCC | V |
A0, A1, A2, P7–P0 | VCC = 1.65 V to 2.7 V | –0.5 | 0.3 × VCC | |||
VCC = 3 V to 5.5 V | –0.5 | 0.2 × VCC | ||||
IOH | High-level output current | Any P-port, P7–P0 | –10 | mA | ||
IOL | Low-level output current(2) | P00-P07, P10-P17 | Tj ≤ 65°C | 25 | mA | |
Tj ≤ 85°C | 18 | |||||
Tj ≤ 100°C | 9 | |||||
INT, SDA | Tj ≤ 85°C | 6 | ||||
Tj ≤ 100°C | 3 | |||||
ICC | Continuous current through GND | All P-ports P7-P0, INT, and SDA | 200 | mA | ||
Continuous current through VCC | All P-ports P7-P0 | –80 | ||||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | TCA9534A | UNIT | ||
---|---|---|---|---|
PW (TSSOP) | DW (SOIC) | |||
16 PINS | 16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 122 | 92.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 56.4 | 53.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 67.1 | 56.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 10.8 | 26.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 66.5 | 56.4 | °C/W |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
VIK | Input diode clamp voltage | II = –18 mA | 1.65 V to 5.5 V | –1.2 | V | |||
VPORR | Power-on reset voltage, VCC rising | VI = VCC or GND, IO = 0 | 1.2 | 1.5 | V | |||
VPORF | Power-on reset voltage, VCC falling | VI = VCC or GND, IO = 0 | 0.75 | 1 | V | |||
VOH | P-port high-level output voltage(2) | IOH = –8 mA | 1.65 V | 1.2 | V | |||
2.3 V | 1.8 | |||||||
3 V | 2.6 | |||||||
4.5 V | 4.1 | |||||||
IOH = –10 mA | 1.65 V | 1 | ||||||
2.3 V | 1.7 | |||||||
3 V | 2.5 | |||||||
4.5 V | 4 | |||||||
IOL | SDA(4) | VOL = 0.4 V | 1.65 V to 5.5 V | 3 | mA | |||
P port(3) | VOL = 0.5 V | 1.65 V to 5.5 V | 8 | |||||
VOL = 0.7 V | 1.65 V to 5.5 V | 10 | ||||||
INT (5) | VOL = 0.4 V | 1.65 V to 5.5 V | 3 | |||||
II | SCL, SDA | VI = VCC or GND | 1.65 V to 5.5 V | ±1 | μA | |||
A2–A0 | ±1 | |||||||
IIH | P port | VI = VCC | 1.65 V to 5.5 V | 1 | μA | |||
IIL | P port | VI = GND | 1.65 V to 5.5 V | –1 | μA | |||
ICC | Operating mode | VI = VCC or GND, IO = 0, I/O = inputs, fscl = 400 kHz, no load |
5.5 V | 22 | 40 | μA | ||
3.6 V | 11 | 30 | ||||||
2.7 V | 8 | 19 | ||||||
1.65 | 5 | 11 | ||||||
Standby mode | VI = GND, IO = 0, I/O = inputs, fscl = 0 kHz, no load |
VI = VCC | 5.5 V | 1.5 | 3.9 | |||
3.6 V | 0.9 | 2.2 | ||||||
2.7 V | 0.6 | 1.8 | ||||||
1.95 V | 0.4 | 1.5 | ||||||
VI = GND | 5.5 V | 1.5 | 8.7 | |||||
3.6 V | 0.9 | 4 | ||||||
2.7 V | 0.6 | 3 | ||||||
1.95 V | 0.4 | 2.2 | ||||||
Ci | SCL | VI = VCC or GND | 1.65 V to 5.5 V | 3 | 8 | pF | ||
Cio | SDA | VIO = VCC or GND | 1.65 V to 5.5 V | 3 | 9.5 | pF | ||
P port | 3.7 | 9.5 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
STANDARD MODE | |||||
fscl | I2C clock frequency | 0 | 100 | kHz | |
tsch | I2C clock high time | 4 | µs | ||
tscl | I2C clock low time | 4.7 | µs | ||
tsp | I2C spike time | 50 | ns | ||
tsds | I2C serial-data setup time | 250 | ns | ||
tsdh | I2C serial-data hold time | 0 | ns | ||
ticr | I2C input rise time | 1000 | ns | ||
ticf | I2C input fall time | 300 | ns | ||
tocf | I2C output fall time | 10-pF to 400-pF bus | 300 | ns | |
tbuf | I2C bus free time between stop and start | 4.7 | µs | ||
tsts | I2C start or repeated start condition setup | 4.7 | µs | ||
tsth | I2C start or repeated start condition hold | 4 | µs | ||
tsps | I2C stop condition setup | 4 | µs | ||
tvd(data) | Valid data time | SCL low to SDA output valid | 3.45 | ns | |
tvd(ack) | Valid data time of ACK condition | ACK signal from SCL low to SDA (out) low |
3.45 | µs | |
Cb | I2C bus capacitive load | 400 | pF | ||
FAST MODE | |||||
fscl | I2C clock frequency | 0 | 400 | kHz | |
tsch | I2C clock high time | 0.6 | µs | ||
tscl | I2C clock low time | 1.3 | µs | ||
tsp | I2C spike time | 50 | ns | ||
tsds | I2C serial-data setup time | 100 | ns | ||
tsdh | I2C serial-data hold time | 0 | ns | ||
ticr | I2C input rise time | 20 | 300 | ns | |
ticf | I2C input fall time | 20 × (VDD / 5.5 V) | 300 | ns | |
tocf | I2C output fall time | 10-pF to 400-pF bus | 20 × (VDD / 5.5 V) | 300 | ns |
tbuf | I2C bus free time between stop and start | 1.3 | µs | ||
tsts | I2C start or repeated start condition setup | 0.6 | µs | ||
tsth | I2C start or repeated start condition hold | 0.6 | µs | ||
tsps | I2C stop condition setup | 0.6 | µs | ||
tvd(data) | Valid data time | SCL low to SDA output valid | 0.9 | ns | |
tvd(ack) | Valid data time of ACK condition | ACK signal from SCL low to SDA (out) low |
0.9 | µs | |
Cb | I2C bus capacitive load | 400 | pF |
PARAMETER | FROM (INPUT) |
TO (OUTPUT) |
MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
STANDARD and FAST MODE | ||||||
tiv | Interrupt valid time | P port | INT | 4 | µs | |
tir | Interrupt reset delay time | SCL | INT | 4 | µs | |
tpv | Output data valid | SCL | P7–P0 | 350 | ns | |
tps | Input data setup time | P port | SCL | 100 | ns | |
tph | Input data hold time | P port | SCL | 1 | μs |