JAJSH54E July   2009  – April 2019 TCA9555

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 5-V Tolerant I/O Ports
      2. 9.3.2 Hardware Address Pins
      3. 9.3.3 Interrupt (INT) Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset (POR)
      2. 9.4.2 Powered-Up
    5. 9.5 Programming
      1. 9.5.1 I/O Port
      2. 9.5.2 I2C Interface
        1. 9.5.2.1 Bus Transactions
          1. 9.5.2.1.1 Writes
          2. 9.5.2.1.2 Reads
      3. 9.5.3 Device Address
      4. 9.5.4 Control Register and Command Byte
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Calculating Junction Temperature and Power Dissipation
        2. 10.2.2.2 Minimizing ICC When I/O Is Used to Control LED
        3. 10.2.2.3 Pull-Up Resistor Calculation
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VIK Input diode clamp voltage II = –18 mA 1.65 V to 5.5 V –1.2 V
VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.65 V to 5.5 V 1.2 1.5 V
VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 1.65 V to 5.5 V 0.75 1 V
VOH P-port high-level output voltage(2) IOH = –8 mA 1.65 V 1.2 V
2.3 V 1.8
3 V 2.6
4.75 V 4.1
IOH = –10 mA 1.65 V 1
2.3 V 1.7
3 V 2.5
4.75 V 4
IOL Low-level output current SDA VOL = 0.4 V 1.65 V to 5.5 V 3 mA
P port(3) VOL = 0.5 V 1.65 V to 5.5 V 8 mA
VOL = 0.7 V 1.65 V to 5.5 V 10 mA
INT VOL = 0.4 V 1.65 V to 5.5 V 3 mA
II Input leakage current SCL, SDA Input leakage VI = VCC or GND 1.65 V to 5.5 V ±1 μA
A2–A0 Input leakage VI = VCC or GND 1.65 V to 5.5 V ±1 μA
IIH Input high leakage current P port VI = VCC 1.65 V to 5.5 V 1 μA
IIL Input low leakage current P port VI = GND 1.65 V to 5.5 V –100 μA
ICC Quiescent current Operating mode IO = 0,
I/O = inputs, fSCL = 400 kHz, tr = 3 ns, No load		 5.5 V 22 40 μA
3.6 V 11 30
2.7 V 8 19
1.95 V 5 11
Standby mode Low inputs VI = GND, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load		 5.5 V 1.1 1.5 mA
3.6 V 0.7 1.3
2.7 V 0.5 1
1.95 V 0.3 0.9
High inputs VI = VCC, IO = 0, I/O = inputs,
fSCL = 0 kHz, No load		 5.5 V 2.5 3.5 μA
3.6 V 1 1.8
2.7 V 0.7 1.6
1.95 V 0.5 1
CI Input capacitance SCL VI = VCC or GND 1.65 V to 5.5 V 3 8 pF
Cio Input-output pin capacitance SDA VIO = VCC or GND 1.65 V to 5.5 V 3 9.5 pF
P port 3.7 9.5
(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
(2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum current of 100 mA, for a device total of 200 mA.
(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).