JAJSH54E July   2009  – April 2019 TCA9555

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 5-V Tolerant I/O Ports
      2. 9.3.2 Hardware Address Pins
      3. 9.3.3 Interrupt (INT) Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset (POR)
      2. 9.4.2 Powered-Up
    5. 9.5 Programming
      1. 9.5.1 I/O Port
      2. 9.5.2 I2C Interface
        1. 9.5.2.1 Bus Transactions
          1. 9.5.2.1.1 Writes
          2. 9.5.2.1.2 Reads
      3. 9.5.3 Device Address
      4. 9.5.4 Control Register and Command Byte
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Calculating Junction Temperature and Power Dissipation
        2. 10.2.2.2 Minimizing ICC When I/O Is Used to Control LED
        3. 10.2.2.3 Pull-Up Resistor Calculation
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.2.3 Pull-Up Resistor Calculation

The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of VCC, VOL,(max), and IOL as shown in Equation 5.

Equation 5. TCA9555 desc_eq1_scps199.gif

The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL = 400 kHz) and bus capacitance, Cb as shown in Equation 6.

Equation 6. TCA9555 desc_eq2_scps204.gif

The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9555, Ci for SCL or Cio for SDA, the capacitance of wires, connections and traces, and the capacitance of additional slaves on the bus. For further details, see the I2C Pull-up Resistor Calculation application report, SLVA689.