JAJSH54E July   2009  – April 2019 TCA9555

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 5-V Tolerant I/O Ports
      2. 9.3.2 Hardware Address Pins
      3. 9.3.3 Interrupt (INT) Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset (POR)
      2. 9.4.2 Powered-Up
    5. 9.5 Programming
      1. 9.5.1 I/O Port
      2. 9.5.2 I2C Interface
        1. 9.5.2.1 Bus Transactions
          1. 9.5.2.1.1 Writes
          2. 9.5.2.1.2 Reads
      3. 9.5.3 Device Address
      4. 9.5.4 Control Register and Command Byte
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Calculating Junction Temperature and Power Dissipation
        2. 10.2.2.2 Minimizing ICC When I/O Is Used to Control LED
        3. 10.2.2.3 Pull-Up Resistor Calculation
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DB, PW Package
24-Pin TSSOP
Top View
RTW, RGE Package
24-Pin WQFN, VQFN with Exposed Thermal Pad
Top View
The exposed thermal pad, if used, must be connected as a secondary ground or left electrically open.

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
DB, PW RTW, RGE
A0 21 18 Input Address input 0. Connect directly to VCC or ground
A1 2 23 Input Address input 1. Connect directly to VCC or ground
A2 3 24 Input Address input 2. Connect directly to VCC or ground
GND 12 9 GND Ground
INT 1 22 Output Interrupt output. Connect to VCC through a pull-up resistor
P00 4 1 I/O P-port I/O. Push-pull design structure. At power on, P00 is configured as an input
P01 5 2 I/O P-port I/O. Push-pull design structure. At power on, P01 is configured as an input
P02 6 3 I/O P-port I/O. Push-pull design structure. At power on, P02 is configured as an input
P03 7 4 I/O P-port I/O. Push-pull design structure. At power on, P03 is configured as an input
P04 8 5 I/O P-port I/O. Push-pull design structure. At power on, P04 is configured as an input
P05 9 6 I/O P-port I/O. Push-pull design structure. At power on, P05 is configured as an input
P06 10 7 I/O P-port I/O. Push-pull design structure. At power on, P06 is configured as an input
P07 11 8 I/O P-port I/O. Push-pull design structure. At power on, P07 is configured as an input
P10 13 10 I/O P-port I/O. Push-pull design structure. At power on, P10 is configured as an input
P11 14 11 I/O P-port I/O. Push-pull design structure. At power on, P11 is configured as an input
P12 15 12 I/O P-port I/O. Push-pull design structure. At power on, P12 is configured as an input
P13 16 13 I/O P-port I/O. Push-pull design structure. At power on, P13 is configured as an input
P14 17 14 I/O P-port I/O. Push-pull design structure. At power on, P14 is configured as an input
P15 18 15 I/O P-port I/O. Push-pull design structure. At power on, P15 is configured as an input
P16 19 16 I/O P-port I/O. Push-pull design structure. At power on, P16 is configured as an input
P17 20 17 I/O P-port I/O. Push-pull design structure. At power on, P17 is configured as an input
SCL 22 19 Input Serial clock bus. Connect to VCC through a pull-up resistor
SDA 23 20 Input Serial data bus. Connect to VCC through a pull-up resistor
VCC 24 21 Supply Supply voltage