JAJSD13B March   2017  – February 2020 TCA9802

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Integrated Current Source
      2. 9.3.2 Ultra-Low Power Consumption
      3. 9.3.3 No Static-Voltage Offset
      4. 9.3.4 Active-High Repeater Enable Input
      5. 9.3.5 Powered Off High Impedance I2C Bus Pins on A-Side
      6. 9.3.6 Powered-Off Back-Power Protection for I2C Bus Pins
      7. 9.3.7 Clock Stretching and Multiple Master Arbitration Support
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Operation Considerations
        1. 9.4.1.1 B-Side Input Low (VIL/IILC/RILC)
          1. 9.4.1.1.1 VILC & IILC
          2. 9.4.1.1.2 RILC
        2. 9.4.1.2 Input and Output Leakage Current (IEXT-I/IEXT-O)
          1. 9.4.1.2.1 IEXT-I
          2. 9.4.1.2.2 IEXT-O
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Selection Guide
      2. 10.1.2 Special Considerations for the B-side
        1. 10.1.2.1 FET or Pass-Gate Translators
        2. 10.1.2.2 Buffered Translators/Level-shifters
    2. 10.2 Typical Application
      1. 10.2.1 Single Device
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Buffering Without Level-Shifting
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Parallel Device Use Case
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
      4. 10.2.4 Series Device Use Case
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
        3. 10.2.4.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
OUTPUT CHARACTERISTICS
VOL Low-level output voltage SDAA, SCLA IOL = 6 mA, VILB = 0 V 0.04 0.13 V
SDAB, SCLB VIA = 0 V 0.22 0.26
IEXT-I(2) Allowed input leakage current of ICS SDAB, SCLB 0 200 µA
IEXT-O(2) Allowed output leakage current of ICS SDAB, SCLB 0 200 µA
ICS Current source value 2.2 mA
Current source tolerance –25 25 %
INPUT CHARACTERISTICS
REN Enable pin pull-up 150 250 450 kΩ
VIH High-level input voltage SDAA, SCLA 0.7 × VCCA VCCA V
SDAB, SCLB(5) 0.7 × VCCB VCCB
EN 0.7 × VCCA VCCA
VIL Low-level input voltage SDAA, SCLA 0 0.3 × VCCA V
SDAB, SCLB(3)(5) 0 0.3 × VCCB
EN 0 0.3 × VCCA
IILC Low-level input current contention SDAB, SCLB(3) 800 µA
RILC Low-level allowed pull-down resistance SDAB, SCLB(5) 150 Ω
CBUS Bus capacitance limit SDAB, SCLB(4) 0 400 pF
DC CHARACTERISTICS
UVLO Under-voltage lock out VCCA VCCA rising and falling; VCCB = 1.65 or 3.6 V 0.3 0.55 0.8 V
VCCB VCCB rising; VCCA = 0.8 or 3.6 V 1.3 1.51 1.6
VCCB falling; VCCA = 0.8 or 3.6 V 1.2 1.4 1.6
ICCA Quiescent supply current for VCCA SDAA = SCLA = VCCA or GND, SDAB = SCLB = open, EN = VCCA VCCA = 0.8 V 0.1 7 µA
VCCA = 1.8 V 0.1 8
VCCA = 2.5 V 0.2 9
VCCA = 3.6 V 0.2 12
ICCB Quiescent supply current for VCCB Both channels high, SDAA = SCLA = pulled up to VCCA, SDAB = SCLB = open, EN = VCCA VCCB = 1.8 V 33 60 µA
VCCB = 2.5 V 36 65
VCCB = 3.6 V 41 75
Both channels low, SDAA = SCLA = GND. SDAB = SCLB = open, EN = VCCA VCCB = 1.8 V 4.3 5.2 mA
VCCB = 2.5 V 4.4 5.2
VCCB = 3.6 V 4.5 5.3
ICCA + ICCB Total quiescent supply current VCCA = VCCB = 1.8 V, SDAA/SCLA = VCCA, SDAB/SCLB = VCCB 34 µA
II Input leakage current SDAA, SCLA VI = VCCA, EN = GND ±10 µA
VI = GND, EN = GND ±10
SDAB, SCLB VCCB = 0 V, VI = 3.6 V ±10
CIO I/O Capacitance SDAA, SCLA VI = 0 V or 3.3 V, f = 1 MHz 2 10 pF
SDAB, SCLB VCCB = GND, VI = 0 V, f = 1 MHz 8
(1) All typical values are at nominal supply voltage (1.8 V) and TA = 25 °C unless otherwise specified.
(2) SDAB, SCLB may not sink current from external sources. It is required that no source of external current be used on these pins for proper device operation due to the internal current source.
(3) VIL specification is for the first low-level seen by the SDAB and SCLB pins. IILC must also be satisfied in order to be interpreted as a low.
(4) SDAB, SCLB have a maximum supported capacitive load for device operation. If this load capacitance maximum is violated, the device does not function properly. SDAA, SCLA have no maximum capacitance limit.
(5) Parameter specified by design. Not tested in production.