JAJSV04A July   2024  – November 2024 TCAN1043N-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings - IEC Specifications
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation Ratings
    7. 5.7  Power Supply Characteristics
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply Pins
        1. 7.3.1.1 VSUP Pin
        2. 7.3.1.2 VCC Pin
        3. 7.3.1.3 VIO Pin
      2. 7.3.2 Digital Inputs and Outputs
        1. 7.3.2.1 TXD Pin
        2. 7.3.2.2 RXD Pin
        3. 7.3.2.3 nFAULT Pin
        4. 7.3.2.4 EN Pin
        5. 7.3.2.5 nSTB Pin
      3. 7.3.3 GND
      4. 7.3.4 INH Pin
      5. 7.3.5 WAKE Pin
      6. 7.3.6 CAN Bus Pins
      7. 7.3.7 Faults
        1. 7.3.7.1 Internal and External Fault Indicators
          1. 7.3.7.1.1 Power-Up (PWRON Flag)
          2. 7.3.7.1.2 Wake-Up Request (WAKERQ Flag)
          3. 7.3.7.1.3 Undervoltage Faults
            1. 7.3.7.1.3.1 Undervoltage on VSUP
            2. 7.3.7.1.3.2 Undervoltage on VCC
            3. 7.3.7.1.3.3 Undervoltage on VIO
          4. 7.3.7.1.4 CAN Bus Fault (CBF Flag)
          5. 7.3.7.1.5 TXD Dominant State Timeout (TXDDTO Flag)
          6. 7.3.7.1.6 TXD Shorted to RXD Fault (TXDRXD Flag)
          7. 7.3.7.1.7 CAN Bus Dominant Fault (CANDOM Flag)
      8. 7.3.8 Local Faults
        1. 7.3.8.1 TXD Dominant Timeout (TXD DTO)
        2. 7.3.8.2 Thermal Shutdown (TSD)
        3. 7.3.8.3 Undervoltage Lockout (UVLO)
        4. 7.3.8.4 Unpowered Devices
        5. 7.3.8.5 Floating Terminals
        6. 7.3.8.6 CAN Bus Short-Circuit Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Mode Description
        1. 7.4.1.1 Normal Mode
        2. 7.4.1.2 Silent Mode
        3. 7.4.1.3 Standby Mode
        4. 7.4.1.4 Go-To-Sleep Mode
        5. 7.4.1.5 Sleep Mode
          1. 7.4.1.5.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 7.4.1.5.2 Local Wake-Up (LWU) via WAKE Input Terminal
      2. 7.4.2 CAN Transceiver
        1. 7.4.2.1 CAN Transceiver Operation
          1. 7.4.2.1.1 CAN Transceiver Modes
            1. 7.4.2.1.1.1 CAN Off Mode
            2. 7.4.2.1.1.2 CAN Autonomous: Inactive and Active
            3. 7.4.2.1.1.3 CAN Active
          2. 7.4.2.1.2 Driver and Receiver Function Tables
          3. 7.4.2.1.3 CAN Bus States
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Design Requirements
        1. 8.1.2.1 Bus Loading, Length and Number of Nodes
      3. 8.1.3 Detailed Design Procedure
        1. 8.1.3.1 CAN Termination
      4. 8.1.4 Application Curves
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.9 Timing Requirements

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Characteristics
tPWRUP Time required for INH active after VSUP ≥ UVSUP(R) See Figure 6-10    500 µs
tUV Undervoltage filter time VCC and VIO (1) VCC ≤ UVCC or VIO ≤ UVIO 100 350 ms
tUV(RE-ENABLE) Re-enable time after undervoltage event (1) Time for device to return to normal operation from a UVCC or UVIO undervoltage event 200 µs
Device Characteristics
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD) Recessive to dominant RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 
See Figure 6-6 		 140 215 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD) Dominant to recessive RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 
See  Figure 6-6		 140 205 ns
tWK(TIMEOUT) Bus wake-up timeout value (1) 0.8 2 ms
tWK(FILTER) Bus time to meet filtered bus requirements for wake-up request (1) 0.5 1.8 µs
tSILENCE Timeout for bus inactivity (1) Timer is reset and restarted, when bus changes from dominant to recessive or vice versa 0.6 1.2 s
tBIAS Bus bias reaction time (1) Measured from the start of a dominant-recessive-dominant sequence (each phase 6 μs) until VSYM ≥ 0.1 nSTB = EN = 0 V, RL = 60 Ω, CSPLIT = 4.7 nF
See Figure 6-9  		 200 µs
tCBF Bus fault-detection time 45 ≤ RCM ≤ 70 Ω
CL = open		 2.5 µs
tWAKE_HT Hold time for which WAKE pin voltage should be stable after the rising or falling edge on WAKE pin to recognize LWU.
 		 5 50 µs
Mode Change Characteristics
tINH_SLP_STB Time after WUP or LWU event until INH asserted (1)  100 µs
tMODE1 Mode change time from leaving the Sleep mode to entering Normal or Silent mode (1) Time measured from VCC and VIO crossing UV thresholds to entering normal or silent mode. 20 µs
tMODE2 Mode change time between normal, silent and standby mode and from sleep to standby mode (1) Mode change time between normal, silent and standby mode and from sleep to standby mode 10 µs
tGOTOSLEEP Minimum hold time for transition to sleep mode (1) EN = H and nSTB = L 20 50 µs
(1) Specified by design and verified via bench characterization