JAJSNI0 December 2021 TCAN1164-Q1
PRODUCTION DATA
The SPI communication uses a standard SPI interface. Physically the digital interface pins are nCS (Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out) and SCLK (Serial Clock). Each SPI transaction is a 16, 24 or 32 bits containing an address and read/write command byte followed by one to three data bytes. The data shifted out on the SDO pin for the transaction always starts with the Global Status Register (byte). This register provides the high level status information about the device status. The two data bytes which are the ‘response’ to the command byte are shifted out next. Data bytes shifted out during a write command is content of the registers prior to the new data being written and updating the registers. Data bytes shifted out during a read command are the content of the registers and the registers is not updated.
The SPI data input data on SDI is sampled on the low to high edge of the clock (SCLK). The SPI output data on SDO is changed on the high to low edge of the clock (SCLK).