JAJSEB2 December 2017 TCAN4420
PRODUCTION DATA.
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PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Driver Electrical Characteristics | |||||||
VO(D) | Bus output voltage (dominant) | CANH | See Figure 8 and Figure 9, TXD = 0 V, RL = 60 Ω, CL = open, RCM = open | 2.75 | 4.5 | V | |
CANL | 0.5 | 2.25 | V | ||||
VO(R) | Bus output voltage (recessive) | See Figure 6 and Figure 9, TXD = VCC, RL = open (no load), RCM = open | 2 | 0.5 x VCC | 3 | V | |
VOD(D) | Differential output voltage (dominant) | See Figure 6 and Figure 9, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 4.75 V ≤ VCC ≤ 5.25 V |
1.5 | 3 | V | ||
See Figure 6 and Figure 9, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 4.5 V ≤ VCC ≤ 5.5 V |
1.3 | 3.2 | V | ||||
VOD(R) | Differential output voltage (recessive) | See Figure 6 and Figure 9, TXD = VCC, RL = 60 Ω, CL = open, RCM = open | –120 | 12 | mV | ||
SeeFigure 6 and Figure 9,TXD = VCC, RL = open, CL = open, RCM = open | –50 | 50 | mV | ||||
VSYM | Output symmetry (dominant or recessive) (VCC - VO(CANH) - VO(CANL)) |
See Figure 6 and Figure 9, RL = 60 Ω, CL = open, RCM = open | –400 | 400 | mV | ||
IOS(DOM) | Short-circuit steady-state output current, Dominant | See Figure 6 and Figure 12, V(CAN_H) ≤ –5 V, CANL = open, TXD = 0 V | –115 | mA | |||
See Figure 6 and Figure 12, V(CAN_L) = 40 V, CANH = open, TXD = 0 V | 115 | mA | |||||
IOS(REC) | Short-circuit steady-state output current, Recessive | See Figure 6 and Figure 12, –27 V ≤ VBUS ≤ 32 V, VBUS = CANH = CANL | –5 | 5 | mA | ||
Receiver Electrical Characteristics | |||||||
VIT | Input threshold voltage | See Figure 10 | 500 | 900 | mV | ||
VHYS | Hysteresis voltage for input threshold | 120 | mV | ||||
VCM | Common Mode Range | –12 | 12 | V | |||
IIOFF(LKG) | Power-off (unpowered) bus input leakage current | CANH = CANL = 5 V, VCC to GND via 0 Ω | 5 | µA | |||
CI | Input capacitance to ground (CANH or CANL) | TXD = VCC = VIO | 40 | pF | |||
CID | Differential input capacitance | 20 | pF | ||||
RID | Differential input resistance | 20 | 80 | kΩ | |||
RIN | Single Ended Input resistance (CANH or CANL) |
10 | 40 | kΩ | |||
RIN(M) | Input resistance matching: [1 – (RIN(CANH) / RIN(CANL))] × 100 % |
V(CAN_H) = V(CAN_L) = 5 V | –1% | 1% | |||
VIO PIN | |||||||
VIO | Supply voltage on VIO pin | 2.8 | 5.5 | V | |||
IIO | Supply current on VIO pin | RXD pin floating, TXD = 0 V | 350 | µA | |||
RXD pin floating, TXD = 5 | 50 | µA | |||||
TXD Terminal (CAN Transmit Data Input) | |||||||
VIH | High-level input voltage | 0.7VIO | V | ||||
VIL | Low-level input voltage | 0.3VIO | V | ||||
IIH | High-level input leakage current | VTXD = VIO = VCC = 5.5 V | –2.5 | 0 | 1 | µA | |
IIL | Low-level input leakage current | VTXD = 0 V, VCC = 5.5 V | –200 | –6 | µA | ||
ILKG(OFF) | Unpowered leakage current | VTXD = 5.5 V, VIO = VCC = 0 V | –1 | 0 | 1 | µA | |
CI | Input Capacitance | VIN = 0.4 x sin(2 x ⫪ x 2 x 106 x t) + 2.5 | 20 | pF | |||
RXD Pin (CAN Receive Data Output) | |||||||
VOH | High-level input voltage | See Figure 10, IO = –2 mA | 0.8VIO | V | |||
VOL | Low-level input voltage | See Figure 10, IO = –2 mA | 0.2VIO | V | |||
ILKG(OFF) | Unpowered leakage current | VRXD = 5.5 V, VIO = VCC = 0 V | –1 | 0 | 1 | µA | |
SW Pin (Polarity Switch Input) | |||||||
VIH | High-level input voltage | 0.7VIO | V | ||||
VIL | Low-level input voltage | 0.3VIO | V | ||||
IIH | High-level input leakage current | SW = VIO = VCC = 5.5 V | 0.5 | 20 | µA | ||
IIL | Low-level input leakage current | SW = 0 V, VCC = 5.5 V | –1 | 1 | µA | ||
ILKG(OFF) | Unpowered leakage current | SW = 5.5 V, VIO = VCC = 0 V | –1 | 0 | 1 | µA |