JAJSGQ7A December 2018 – January 2020 TCAN4550
PRODUCTION DATA.
The MRAM and start address for this register, EFSA, has special consideration.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RSVD | EFWM[5:0] | ||||||
R | RP | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RSVD | EFS[5:0] | ||||||
R | RP | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EFSA[15:8] | |||||||
RP | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EFSA[7:0] | |||||||
RP |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:30 | RSVD | R | 0x0 | Reserved |
29:24 | EFWM[5:0] | RP | 0x0 | Event FIFO Watermark
0 - Watermark interrupt disabled 1-32 - Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32 - Watermark interrupt disabled |
23:22 | RSVD | R | 0x0 | Reserved |
21:16 | EFS[5:0] | RP | 0x0 | Event FIFO Size
0 - Tx Event FIFO disabled 1-32 - Number of Tx Event FIFO elements >32 - Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS - 1 |
15:0 | EFSA[15:0] | RP | 0x0 | Event FIFO Start Address
Start address of Tx Event FIFO in Message RAM |