JAJSGQ7A December 2018 – January 2020 TCAN4550
PRODUCTION DATA.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RSVD | |||||||
R | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RSVD | |||||||
R | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TSC[15:8] | |||||||
RC | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSC[7:0] | |||||||
RC |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | RSVD | R | 0x0 | Reserved |
23:20 | RSVD | R | 0x0 | Reserved |
15:8 | TSC[7:0] | RC | 0x0 | Timestamp Counter
The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. |
7:0 | TSC[7:0] | RC | 0x0 | Timestamp Counter
The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. |