SPRS969G August 2016 – November 2019 TDA2EG-17
PRODUCTION DATA.
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Table 5-27 summarizes the DLL characteristics and assumes testing over recommended operating conditions.
NAME | DESCRIPTION | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
finput | Input clock frequency (EMIF_DLL_FCLK) | 333 | MHz | ||
tlock | Lock time | 50k | cycles | ||
trelock | Relock time (a change of the DLL frequency implies that DLL must relock) | 50k | cycles |