SPRS969G
August 2016 – November 2019
TDA2EG-17
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Pin Attributes
4.3
Signal Descriptions
4.3.1
VIP
4.3.2
DSS
4.3.3
HDMI
4.3.4
CSI2
4.3.5
EMIF
4.3.6
GPMC
4.3.7
Timers
4.3.8
I2C
4.3.9
UART
4.3.10
McSPI
4.3.11
QSPI
4.3.12
McASP
4.3.13
USB
4.3.14
PCIe
4.3.15
DCAN
4.3.16
GMAC_SW
4.3.17
eMMC/SD/SDIO
4.3.18
GPIO
4.3.19
PWM
4.3.20
Emulation and Debug Subsystem
4.3.21
System and Miscellaneous
4.3.21.1
Sysboot
4.3.21.2
Power, Reset, and Clock Management (PRCM)
4.3.21.3
System Direct Memory Access (SDMA)
4.3.21.4
Interrupt Controllers (INTC)
4.3.22
Power Supplies
4.4
Pin Multiplexing
4.5
Connections for Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Power on Hour (POH) Limits
5.4
Recommended Operating Conditions
5.5
Operating Performance Points
5.5.1
AVS and ABB Requirements
5.5.2
Voltage And Core Clock Specifications
5.5.3
Maximum Supported Frequency
5.6
Power Consumption Summary
5.7
Electrical Characteristics
Table 5-6
LVCMOS DDR DC Electrical Characteristics
Table 5-7
Dual Voltage LVCMOS I2C DC Electrical Characteristics
Table 5-8
IQ1833 Buffers DC Electrical Characteristics
Table 5-9
IHHV1833 Buffers DC Electrical Characteristics
Table 5-10
LVCMOS CSI2 DC Electrical Characteristics
Table 5-11
Dual Voltage SDIO1833 DC Electrical Characteristics
Table 5-12
Dual Voltage LVCMOS DC Electrical Characteristics
5.7.1
USBPHY DC Electrical Characteristics
5.7.2
HDMIPHY DC Electrical Characteristics
5.7.3
PCIEPHY DC Electrical Characteristics
5.8
VPP Specifications for One-Time Programmable (OTP) eFuses
Table 5-13
Recommended Operating Conditions for OTP eFuse Programming
5.8.1
Hardware Requirements
5.8.2
Programming Sequence
5.8.3
Impact to Your Hardware Warranty
5.9
Thermal Resistance Characteristics for CBD Package
5.9.1
Package Thermal Characteristics
5.10
Timing Requirements and Switching Characteristics
5.10.1
Timing Parameters and Information
5.10.1.1
Parameter Information
5.10.1.1.1
1.8 V and 3.3 V Signal Transition Levels
5.10.1.1.2
1.8 V and 3.3 V Signal Transition Rates
5.10.1.1.3
Timing Parameters and Board Routing Analysis
5.10.2
Interface Clock Specifications
5.10.2.1
Interface Clock Terminology
5.10.2.2
Interface Clock Frequency
5.10.3
Power Supply Sequences
5.10.4
Clock Specifications
5.10.4.1
Input Clocks / Oscillators
5.10.4.1.1
OSC0 External Crystal
5.10.4.1.2
OSC0 Input Clock
5.10.4.1.3
Auxiliary Oscillator OSC1 Input Clock
5.10.4.1.3.1
OSC1 External Crystal
5.10.4.1.3.2
OSC1 Input Clock
5.10.4.1.4
RC On-die Oscillator Clock
5.10.4.2
Output Clocks
5.10.4.3
DPLLs, DLLs
5.10.4.3.1
DPLL Characteristics
5.10.4.3.2
DLL Characteristics
5.10.4.3.3
DPLL and DLL Noise Isolation
5.10.5
Recommended Clock and Control Signal Transition Behavior
5.10.6
Peripherals
5.10.6.1
Timing Test Conditions
5.10.6.2
Virtual and Manual I/O Timing Modes
5.10.6.3
VIP
5.10.6.4
DSS
5.10.6.5
HDMI
5.10.6.6
CSI2
5.10.6.6.1
CSI-2 MIPI D-PHY
5.10.6.7
EMIF
5.10.6.8
GPMC
5.10.6.8.1
GPMC/NOR Flash Interface Synchronous Timing
5.10.6.8.2
GPMC/NOR Flash Interface Asynchronous Timing
5.10.6.8.3
GPMC/NAND Flash Interface Asynchronous Timing
5.10.6.9
Timers
5.10.6.10
I2C
Table 5-55
Timing Requirements for I2C Input Timings
Table 5-56
Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
Table 5-57
Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
5.10.6.11
UART
Table 5-58
Timing Requirements for UART
Table 5-59
Switching Characteristics Over Recommended Operating Conditions for UART
5.10.6.12
McSPI
5.10.6.13
QSPI
5.10.6.14
McASP
Table 5-66
Timing Requirements for McASP1
Table 5-67
Timing Requirements for McASP2
Table 5-68
Timing Requirements for McASP3/4/5/6/7/8
5.10.6.15
USB
5.10.6.15.1
USB1 DRD PHY
5.10.6.15.2
USB2 PHY
5.10.6.16
USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
5.10.6.17
PCIe3
5.10.6.18
DCAN
Table 5-86
Timing Requirements for DCANx Receive
Table 5-87
Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
5.10.6.19
GMAC_SW
5.10.6.19.1
GMAC MII Timings
Table 5-88
Timing Requirements for miin_rxclk - MII Operation
Table 5-89
Timing Requirements for miin_txclk - MII Operation
Table 5-90
Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
Table 5-91
Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
5.10.6.19.2
GMAC MDIO Interface Timings
5.10.6.19.3
GMAC RMII Timings
Table 5-96
Timing Requirements for GMAC REF_CLK - RMII Operation
Table 5-97
Timing Requirements for GMAC RMIIn Receive
Table 5-98
Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
Table 5-99
Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
5.10.6.19.4
GMAC RGMII Timings
Table 5-103
Timing Requirements for rgmiin_rxc - RGMIIn Operation
Table 5-104
Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
Table 5-105
Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
Table 5-106
Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
5.10.6.20
eMMC/SD/SDIO
5.10.6.20.1
MMC1—SD Card Interface
5.10.6.20.1.1
Default speed, 4-bit data, SDR, half-cycle
5.10.6.20.1.2
High speed, 4-bit data, SDR, half-cycle
5.10.6.20.1.3
SDR12, 4-bit data, half-cycle
5.10.6.20.1.4
SDR25, 4-bit data, half-cycle
5.10.6.20.1.5
UHS-I SDR50, 4-bit data, half-cycle
5.10.6.20.1.6
UHS-I SDR104, 4-bit data, half-cycle
5.10.6.20.1.7
UHS-I DDR50, 4-bit data
5.10.6.20.2
MMC2 — eMMC
5.10.6.20.2.1
Standard JC64 SDR, 8-bit data, half cycle
5.10.6.20.2.2
High-speed JC64 SDR, 8-bit data, half cycle
5.10.6.20.2.3
High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
5.10.6.20.2.4
High-speed JC64 DDR, 8-bit data
Table 5-131
Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
5.10.6.20.3
MMC3 and MMC4—SDIO/SD
5.10.6.20.3.1
MMC3 and MMC4, SD Default Speed
5.10.6.20.3.2
MMC3 and MMC4, SD High Speed
5.10.6.20.3.3
MMC3 and MMC4, SD and SDIO SDR12 Mode
5.10.6.20.3.4
MMC3 and MMC4, SD SDR25 Mode
5.10.6.20.3.5
MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
5.10.6.21
GPIO
5.10.6.22
System and Miscellaneous interfaces
5.10.7
Emulation and Debug Subsystem
5.10.7.1
IEEE 1149.1 Standard-Test-Access Port (JTAG)
5.10.7.1.1
JTAG Electrical Data/Timing
Table 5-153
Timing Requirements for IEEE 1149.1 JTAG
Table 5-154
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
Table 5-155
Timing Requirements for IEEE 1149.1 JTAG With RTCK
Table 5-156
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
5.10.7.2
Trace Port Interface Unit (TPIU)
5.10.7.2.1
TPIU PLL DDR Mode
6
Detailed Description
6.1
Description
6.2
Functional Block Diagram
6.3
MPU
6.4
DSP Subsystem
6.5
IVA
6.6
IPU
6.7
GPU
6.8
BB2D
6.9
Memory Subsystem
6.9.1
EMIF
6.9.2
GPMC
6.9.3
ELM
6.9.4
OCMC
6.10
Interprocessor Communication
6.10.1
MailBox
6.10.2
Spinlock
6.11
Interrupt Controller
6.12
EDMA
6.13
Peripherals
6.13.1
VIP
6.13.2
DSS
6.13.3
Timers
6.13.3.1
General-Purpose Timers
6.13.3.2
32-kHz Synchronized Timer (COUNTER_32K)
6.13.3.3
Watchdog Timer
6.13.4
I2C
6.13.5
UART
6.13.5.1
UART Features
6.13.5.2
IrDA Features
6.13.5.3
CIR Features
6.13.6
McSPI
6.13.7
QSPI
6.13.8
McASP
6.13.9
USB
6.13.10
PCIe
6.13.11
DCAN
6.13.12
GMAC_SW
6.13.13
eMMC/SD/SDIO
6.13.14
GPIO
6.13.15
ePWM
6.13.16
eCAP
6.13.17
eQEP
6.14
On-chip Debug
7
Applications, Implementation, and Layout
7.1
Introduction
7.1.1
Initial Requirements and Guidelines
7.2
Power Optimizations
7.2.1
Step 1: PCB Stack-up
7.2.2
Step 2: Physical Placement
7.2.3
Step 3: Static Analysis
7.2.3.1
PDN Resistance and IR Drop
7.2.4
Step 4: Frequency Analysis
7.2.5
System ESD Generic Guidelines
7.2.5.1
System ESD Generic PCB Guideline
7.2.5.2
Miscellaneous EMC Guidelines to Mitigate ESD Immunity
7.2.5.3
ESD Protection System Design Consideration
7.2.6
EMI / EMC Issues Prevention
7.2.6.1
Signal Bandwidth
7.2.6.2
Signal Routing
7.2.6.2.1
Signal Routing—Sensitive Signals and Shielding
7.2.6.2.2
Signal Routing—Outer Layer Routing
7.2.6.3
Ground Guidelines
7.2.6.3.1
PCB Outer Layers
7.2.6.3.2
Metallic Frames
7.2.6.3.3
Connectors
7.2.6.3.4
Guard Ring on PCB Edges
7.2.6.3.5
Analog and Digital Ground
7.3
Core Power Domains
7.3.1
General Constraints and Theory
7.3.2
Voltage Decoupling
7.3.3
Static PDN Analysis
7.3.4
Dynamic PDN Analysis
7.3.5
Power Supply Mapping
7.3.6
DPLL Voltage Requirement
7.3.7
Loss of Input Power Event
7.3.8
Example PCB Design
7.3.8.1
Example Stack-up
7.3.8.2
vdd Example Analysis
7.4
Single-Ended Interfaces
7.4.1
General Routing Guidelines
7.4.2
QSPI Board Design and Layout Guidelines
7.5
Differential Interfaces
7.5.1
General Routing Guidelines
7.5.2
USB 2.0 Board Design and Layout Guidelines
7.5.2.1
Background
7.5.2.2
USB PHY Layout Guide
7.5.2.2.1
General Routing and Placement
7.5.2.2.2
Specific Guidelines for USB PHY Layout
7.5.2.2.2.1
Analog, PLL, and Digital Power Supply Filtering
7.5.2.2.2.2
Analog, Digital, and PLL Partitioning
7.5.2.2.2.3
Board Stackup
7.5.2.2.2.4
Cable Connector Socket
7.5.2.2.2.5
Clock Routings
7.5.2.2.2.6
Crystals/Oscillator
7.5.2.2.2.7
DP/DM Trace
7.5.2.2.2.8
DP/DM Vias
7.5.2.2.2.9
Image Planes
7.5.2.2.2.10
Power Regulators
7.5.2.3
References
7.5.3
USB 3.0 Board Design and Layout Guidelines
7.5.3.1
USB 3.0 interface introduction
7.5.3.2
USB 3.0 General routing rules
7.5.4
HDMI Board Design and Layout Guidelines
7.5.4.1
HDMI Interface Schematic
7.5.4.2
TMDS General Routing Guidelines
7.5.4.3
TPD5S115
7.5.4.4
HDMI ESD Protection Device (Required)
7.5.4.5
PCB Stackup Specifications
7.5.4.6
Grounding
7.5.5
PCIe Board Design and Layout Guidelines
7.5.5.1
PCIe Connections and Interface Compliance
7.5.5.1.1
Coupling Capacitors
7.5.5.1.2
Polarity Inversion
7.5.5.2
Non-standard PCIe connections
7.5.5.2.1
PCB Stackup Specifications
7.5.5.2.2
Routing Specifications
7.5.5.2.2.1
Impedance
7.5.5.2.2.2
Differential Coupling
7.5.5.2.2.3
Pair Length Matching
7.5.5.3
LJCB_REFN/P Connections
7.5.6
CSI2 Board Design and Routing Guidelines
7.5.6.1
CSI2_0 MIPI CSI-2 (1.5 Gbps)
7.5.6.1.1
General Guidelines
7.5.6.1.2
Length Mismatch Guidelines
7.5.6.1.2.1
CSI2_0 MIPI CSI-2 (1.5 Gbps)
7.5.6.1.3
Frequency-domain Specification Guidelines
7.6
Clock Routing Guidelines
7.6.1
Oscillator Ground Connection
7.7
DDR3 Board Design and Layout Guidelines
7.7.1
DDR3 General Board Layout Guidelines
7.7.2
DDR3 Board Design and Layout Guidelines
7.7.2.1
Board Designs
7.7.2.2
DDR3 EMIF
7.7.2.3
DDR3 Device Combinations
7.7.2.4
DDR3 Interface Schematic
7.7.2.4.1
32-Bit DDR3 Interface
7.7.2.4.2
16-Bit DDR3 Interface
7.7.2.5
Compatible JEDEC DDR3 Devices
7.7.2.6
PCB Stackup
7.7.2.7
Placement
7.7.2.8
DDR3 Keepout Region
7.7.2.9
Bulk Bypass Capacitors
7.7.2.10
High-Speed Bypass Capacitors
7.7.2.10.1
Return Current Bypass Capacitors
7.7.2.11
Net Classes
7.7.2.12
DDR3 Signal Termination
7.7.2.13
VREF_DDR Routing
7.7.2.14
VTT
7.7.2.15
CK and ADDR_CTRL Topologies and Routing Definition
7.7.2.15.1
Four DDR3 Devices
7.7.2.15.1.1
CK and ADDR_CTRL Topologies, Four DDR3 Devices
7.7.2.15.1.2
CK and ADDR_CTRL Routing, Four DDR3 Devices
7.7.2.15.2
Two DDR3 Devices
7.7.2.15.2.1
CK and ADDR_CTRL Topologies, Two DDR3 Devices
7.7.2.15.2.2
CK and ADDR_CTRL Routing, Two DDR3 Devices
7.7.2.15.3
One DDR3 Device
7.7.2.15.3.1
CK and ADDR_CTRL Topologies, One DDR3 Device
7.7.2.15.3.2
CK and ADDR/CTRL Routing, One DDR3 Device
7.7.2.16
Data Topologies and Routing Definition
7.7.2.16.1
DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
7.7.2.16.2
DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
7.7.2.17
Routing Specification
7.7.2.17.1
CK and ADDR_CTRL Routing Specification
7.7.2.17.2
DQS and DQ Routing Specification
8
Device and Documentation Support
8.1
Device Nomenclature
8.1.1
Standard Package Symbolization
8.1.2
Device Naming Convention
8.2
Tools and Software
8.3
Documentation Support
8.4
Related Links
8.5
Support Resources
8.6
Trademarks
8.7
Electrostatic Discharge Caution
8.8
Glossary
9
Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
CBD|538
サーマルパッド・メカニカル・データ
発注情報
sprs969g_oa
5.10.6
Peripherals