JAJSGK9F December 2015 – May 2019 TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX
PRODUCTION DATA.
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Table 7-104 and Table 7-105 present Timing requirements and Switching characteristics for MMC2 - Standard SDR in receiver and Transmitter mode (see Figure 7-68 and Figure 7-69).
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SSDR5 | tsu(cmdV-clkH) | Setup time, mmc2_cmd valid before mmc2_clk rising clock edge | 13.19 | ns | |
SSDR6 | th(clkH-cmdV) | Hold time, mmc2_cmd valid after mmc2_clk rising clock edge | 8.4 | ns | |
SSDR7 | tsu(dV-clkH) | Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge | 13.19 | ns | |
SSDR8 | th(clkH-dV) | Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge | 8.4 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SSDR1 | fop(clk) | Operating frequency, mmc2_clk | 24 | MHz | |
SSDR2H | tw(clkH) | Pulse duration, mmc2_clk high | 0.5*P-0.172 (1) | ns | |
SSDR2L | tw(clkL) | Pulse duration, mmc2_clk low | 0.5*P-0.172 (1) | ns | |
SSDR3 | td(clkL-cmdV) | Delay time, mmc2_clk falling clock edge to mmc2_cmd transition | -16.96 | 16.96 | ns |
SSDR4 | td(clkL-dV) | Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition | -16.96 | 16.96 | ns |