JAJSGK9F December 2015 – May 2019 TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX
PRODUCTION DATA.
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The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 8-45. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in Table 8-46.
LAYER | TYPE | DESCRIPTION |
---|---|---|
1 | Signal | Top routing mostly vertical |
2 | Plane | Ground |
3 | Plane | Split power plane |
4 | Plane | Split power plane or Internal routing |
5 | Plane | Ground |
6 | Signal | Bottom routing mostly horizontal |
NO. | PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
PS1 | PCB routing/plane layers | 6 | |||
PS2 | Signal routing layers | 3 | |||
PS3 | Full ground reference layers under DDR3 routing region(1) | 1 | |||
PS4 | Full 1.5-V power reference layers under the DDR3 routing region(1) | 1 | |||
PS5 | Number of reference plane cuts allowed within DDR routing region(2) | 0 | |||
PS6 | Number of layers between DDR3 routing layer and reference plane(3) | 0 | |||
PS7 | PCB routing feature size | 4 | Mils | ||
PS8 | PCB trace width, w | 4 | Mils | ||
PS9 | Single-ended impedance, Zo | 50 | 75 | Ω | |
PS10 | Impedance control(5) | Z-5 | Z | Z+5 | Ω |