JAJSGK9 データシート

JAJSGK9F December 2015 – May 2019 TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

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6.3.1 DPLL Characteristics

The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next paragraph.

The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock, CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through an asynchronous multplexing.

For more information, see the Power Reset Controller Management chapter of the Device TRM.

Table 6-12 summarizes DPLL type described in Section 6.3, DPLLs, DLLs Specifications introduction.

Table 6-12 DPLL Control Type

DPLL NAME	TYPE	CONTROLLED BY PRCM
DPLL_ABE	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_CORE	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_DEBUGSS	Table 6-13 (Type A)	No^⁽²⁾
DPLL_DSP	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_EVE	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_GMAC	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_HDMI	Table 6-14 (Type B)	No^⁽²⁾
DPLL_IVA	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_MPU	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_PER	Table 6-13 (Type A)	Yes^⁽¹⁾
APLL_PCIE	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_PCIE_REF	Table 6-14 (Type B)	Yes^⁽¹⁾
DPLL_SATA	Table 6-14 (Type B)	No^⁽²⁾
DPLL_USB	Table 6-14 (Type B)	Yes^⁽¹⁾
DPLL_USB_OTG_SS	Table 6-14 (Type B)	No^⁽²⁾
DPLL_VIDEO1	Table 6-13 (Type A)	No^⁽²⁾
DPLL_VIDEO2	Table 6-13 (Type A)	No^⁽²⁾
DPLL_DDR	Table 6-13 (Type A)	Yes^⁽¹⁾
DPLL_GPU	Table 6-13 (Type A)	Yes^⁽¹⁾

DPLL is in the always-on domain.
DPLL is not controlled by the PRCM.

Table 6-13 and Table 6-14 summarize the DPLL characteristics and assume testing over recommended operating conditions.

Table 6-13 DPLL Type A Characteristics

NAME	DESCRIPTION	MIN	MAX	UNIT	COMMENTS
f_input	CLKINP input frequency	0.032	52	MHz	F_INP
f_internal	Internal reference frequency	0.15	52	MHz	REFCLK
f_CLKINPHIF	CLKINPHIF input frequency	10	1400	MHz	F_INPHIF
f_CLKINPULOW	CLKINPULOW input frequency	0.001	600	MHz	Bypass mode: f_CLKOUT = f_CLKINPULOW / (M1 + 1) if ulowclken = 1^⁽⁷⁾
f_CLKOUT	CLKOUT output frequency	20^⁽¹⁾	1800^⁽³⁾	MHz	[M / (N + 1)] × F_INP × [1 / M2] (in locked condition)
f_CLKOUTx2	CLKOUTx2 output frequency	40^⁽¹⁾	2200^⁽³⁾	MHz	2 × [M / (N + 1)] × F_INP × [1 / M2] (in locked condition)
f_CLKOUTHIF	CLKOUTHIF output frequency	20^⁽⁴⁾	1400^⁽⁵⁾	MHz	F_INPHIF / M3 if clkinphifsel = 1
f_CLKOUTHIF	CLKOUTHIF output frequency	40^⁽⁴⁾	2200^⁽⁵⁾	MHz	2 × [M / (N + 1)] × F_INP × [1 / M3] if clkinphifsel = 0
f_CLKDCOLDO	DCOCLKLDO output frequency	40	2800	MHz	2 × [M / (N + 1)] × F_INP (in locked condition)
t_lock	Frequency lock time		6 + 350 × REFCLK	µs
p_lock	Phase lock time		6 + 500 × REFCLK	µs
t_relock-L	Relock time—Frequency lock⁽⁶⁾ (LP relock time from bypass)		6 + 70 × REFCLK	µs	DPLL in LP relock time: lowcurrstdby = 1
p_relock-L	Relock time—Phase lock⁽⁶⁾ (LP relock time from bypass)		6 + 120 × REFCLK	µs	DPLL in LP relock time: lowcurrstdby = 1
t_relock-F	Relock time—Frequency lock⁽⁶⁾ (fast relock time from bypass)		3.55 + 70 × REFCLK	µs	DPLL in fast relock time: lowcurrstdby = 0
p_relock-F	Relock time—Phase lock⁽⁶⁾ (fast relock time from bypass)		3.55 + 120 × REFCLK	µs	DPLL in fast relock time: lowcurrstdby = 0

The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.

For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.

The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down by factor of M3.
The maximum frequency on CLKOUTHIF is assuming M3 = 1.
Relock time assumes typical operating conditions, 10°C maximum temperature drift.
Bypass mode: f_CLKOUT = F_INP if ulowclken = 0. For more information, see the Device TRM.

Table 6-14 DPLL Type B Characteristics

NAME	DESCRIPTION	MIN	MAX	UNIT	COMMENTS
f_input	CLKINP input clock frequency	0.62	60	MHz	F_INP
f_internal	REFCLK internal reference clock frequency	0.62	2.5	MHz	[1 / (N + 1)] × F_INP
f_CLKINPULOW	CLKINPULOW bypass input clock frequency	0.001	600	MHz	Bypass mode: f_CLKOUT = f_CLKINPULOW / (M1 + 1) If ulowclken = 1^⁽⁵⁾
f_CLKLDOOUT	CLKOUTLDO output clock frequency	20^{⁽¹⁾⁽⁶⁾}	2500^{⁽³⁾⁽⁶⁾}	MHz	M / (N + 1)] × F_INP × [1 / M2] (in locked condition)
f_CLKOUT	CLKOUT output clock frequency	20^{⁽¹⁾⁽⁶⁾}	1450^{⁽³⁾⁽⁶⁾}	MHz	[M / (N + 1)] × F_INP × [1 / M2] (in locked condition)
f_CLKDCOLDO	Internal oscillator (DCO) output clock frequency	750^⁽⁶⁾	1500^⁽⁶⁾	MHz	[M / (N + 1)] × F_INP (in locked condition)
f_CLKDCOLDO	Internal oscillator (DCO) output clock frequency	1250^⁽⁶⁾	2500^⁽⁶⁾	MHz	[M / (N + 1)] × F_INP (in locked condition)
t_J	CLKOUTLDO period jitter	–2.5%	2.5%		The period jitter at the output clocks is ± 2.5% peak to peak
	CLKOUT period jitter
	CLKDCOLDO period jitter
t_lock	Frequency lock time		350 × REFCLKs	µs
p_lock	Phase lock time		500 × REFCLKs	µs
t_relock-L	Relock time—Frequency lock⁽⁴⁾ (LP relock time from bypass)		9 + 30 × REFCLKs	µs
p_relock-L	Relock time—Phase lock⁽⁴⁾ (LP relock time from bypass)		9 + 125 × REFCLKs	µs

The minimum frequency on CLKOUT is assuming M2 = 1.

For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.

The maximum frequency on CLKOUT is assuming M2 = 1.
Relock time assumes typical operating conditions, 10°C maximum temperature drift.
Bypass mode: f_CLKOUT = F_INP if ULOWCLKEN = 0. For more information, see the Device TRM.
For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.