JAJSGK9F December 2015 – May 2019 TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX
PRODUCTION DATA.
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Table 7-93 and Table 7-94 present Timing requirements and Switching characteristics for MMC1 - SDR12 in receiver and transmitter mode(see Figure 7-58 and Figure 7-59).
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
SDR125 | tsu(cmdV-clkH) | Setup time, mmc1_cmd valid before mmc1_clk rising clock edge | 25.99 | ns | ||
SDR126 | th(clkH-cmdV) | Hold time, mmc1_cmd valid after mmc1_clk rising clock edge | Pad Loopback Clock | 1.6 | ns | |
Internal Loopback Clock | 1.6 | ns | ||||
SDR127 | tsu(dV-clkH) | Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge | 25.99 | ns | ||
SDR128 | th(clkH-dV) | Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge | Pad Loopback Clock | 1.6 | ns | |
Internal Loopback Clock | 1.6 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SDR120 | fop(clk) | Operating frequency, mmc1_clk | 24 | MHz | |
SDR121 | tw(clkH) | Pulse duration, mmc1_clk high | 0.5*P-0.185 (1) | ns | |
SDR122 | tw(clkL) | Pulse duration, mmc1_clk low | 0.5*P-0.185 (1) | ns | |
SDR123 | td(clkL-cmdV) | Delay time, mmc1_clk falling clock edge to mmc1_cmd transition | -19.13 | 16.93 | ns |
SDR124 | td(clkL-dV) | Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition | -19.13 | 16.93 | ns |