5.9 Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation.

Figure 5-1 through Figure 5-5 and associated notes describes the device Recommended Power Sequencing.

Figure 5-1 Power-Up Sequencing

1. Grey shaded areas are windows where it is valid to ramp-up a voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp-up possibilities based on whether I/O voltage levels are 1.8V or 3.3V (see associated note for more details).
3. vdds18v_* and vdda_* rails should not be combined for best performance to avoid transient switching noise impacts on analog domains. vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation.
4. vdds_ddr* should not ramp-up before vdds18v_*. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation. vdds_ddr* can ramp-up before, concurrently or after vdda_*, there are no dependencies between vdds_ddr* and vdda_* domains.
   • vdds_ddr* supplies can be combined with vdds18v_* and vdds18v_ddr supplies for DDR2 mode of operation (1.8V) and ramped up together for simplified power sequencing.
   • If vdds18v_ddr and vdds_ddr* are kept separate from vdds18v_* on board, then this combined DDR supply can come up together or after the vdds18v_* supply. The DDR supply in this case should never ramp up before the vdds18v_*.
5. vdd should not ramp-up before vdds18v_* or vdds_ddr* domains.
6. vdd_dspeve must not exceed vdd core supply and maintain at least 150mV lower voltage on vdd_dspeve vs vdd. vdd_dspeve could ramp concurrently with vdd if design ensures final operational voltage will not be reached until after vdd and maintains minimum of 150mV less than vdd during entire ramp time. The preferred sequence is to follow vdd to ensure circuit components and PCB design do not cause an inadvertent violation.
7. If any of the vddshv[1-6] power rails are used for 1.8V I/O signaling, then these rails can be combined with vdds18v_*.
   If 3.3V I/O signaling is required, then these rails must be the last to ramp following vdd_dspeve.
8. resetn and porz must remain asserted low for a minimum of 12P⁽¹²⁾ after xi_osc0 is stable at a valid frequency.
9. Setup time: SYSBOOT[15:0] pins must be valid 2P⁽¹²⁾ before porz is de-asserted high.
10. Hold time: SYSBOOT[15:0] pins must be valid 15P⁽¹²⁾ after porz is de-asserted high.
11. resetn to rstoutn delay is 2ms.
12. P = 1/(SYS_CLK1/610) frequency in ns.
13. Ramped Up is defined as reaching the minimum operational voltage level for the corresponding power domain. For information about voltage levels, refer to , Recommended Operating Conditions.

Figure 5-2 Recommended Power-Down Sequencing

1. T1 ≥ 100 µs; T2 = 500 µs; T3 = 1.0 ms; T4 = 1.5 ms; V1 = 2.7 V. All "Tn" markers are intended to show total elapsed time, not interval times.
2. Terminology:
   • V_{OPR MIN} = Minimum Operational Voltage level that ensures device functionality and specified performance in , Recommended Operating Conditions.
   • V_OFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.
   • Ramp Down = transition time from V_{OPR MIN} to V_OFF and is slew rate independent.
3. General timing diagram items:
   • Grey shaded areas show valid transition times for supplies between V_{OPR MIN} and V_OFF.
   • Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
   • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
4. porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
5. vddshv[1-6] domains supplied by 3.3 V:
   • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.
   • must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.
   • must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-3, "vdds18v versus vddshv[1-6] Discharge Relationship".
6. vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
7. vdd_dspeve domain can ramp down before or concurrently with vdd.
8. vdd must ramp down after or concurrently with vdd_dspeve.
9. vdds_ddr[1-3] domains:
   • should ramp down after vdd begins ramping down.
   • If DDR2 memory is used (requiring 1.8V supply),
     • then vdds_ddr[1-3] can be combined with vdds18v and vdds18v_ddr[1-3] domains and sourced from a common supply. Accordingly, all domains can ramp down concurrently with vdds18v.
     • if vdds_ddr[1-3] and vdds18v_ddr[1-3] are combined but kept separate from vdds18v, then the combined 1.8V DDR supply can ramp down before or concurrently with vdds18v.
10. vdda_* domains:
    • can ramp down before, concurrently or after vdds_ddr[1-3], there is no dependency between these supplies.
    • can ramp down before or concurrently with vdds18v.
    • must satisfy the vdds18v versus vdda_* discharge relationship (see Figure 5-5) if any of the vdda_* disable point is later or discharge rate is slower than vdds18v.
11. vdds18v domain:
    • should maintain V_{OPR MIN} (V_NOM -5% = 1.71 V) until all other supplies start to ramp down.
    • must satisfy the vdds18v versus vddshv[1-6] discharge relationship (see Figure 5-3) if any of the vddshv[1-6] is operating at 3.3 V.
    • must satisfy the vdds18v versus vdds_ddr[1-3] discharge relationship (see Figure 5-4) if vdds_ddr[1-3] discharge rate is slower than vdds18v.

Figure 5-3 describes vddshv[1-6] supplies falling before vdds18v supplies delta.

Figure 5-3 vdds18v versus vddshv[1-6] Discharge Relationship

1. Vdelta MAX = 2V

If vdds18v and vdds_ddr* are disabled at the same time due to a loss of input power event or if vdds_ddr* discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr* dropping below 0.6 V is less than 10 ms (Figure 5-4).

Figure 5-4 vdds18v and vdds_ddr* Discharge Relationship⁽¹⁾

1. V1 > 1.0 V; V2 < 0.6 V; T1 < 10 ms.

Figure 5-5 vdds18v and vdda_* Discharge Relationship⁽³⁾

1. vdda_* can be ≥ vdds18v, until vdds18v drops below 1.62 V.
2. vdds18v must be ≥ vdda_*, until vdds18v reaches 0.6 V.
3. V1 = 1.62 V; V2 < 0.6 V.

Figure 5-3 through Figure 5-6 and associated notes described the device Abrupt Power Down Sequence.

A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally, the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of elapsed time. This is the typical range of elapsed time available following a loss of power event, see Section 8.3.7, Loss of Input Power Event for design recommendations. If sufficient elapse time is not provided, then an “abrupt” power-down sequence can be supported without impacting POH reliability if all of the following conditions are met (Figure 5-6).

Figure 5-6 Abrupt Power-Down Sequencing⁽¹⁾

1. V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; T_delta1 > 100 µs; T_delta2 < 10 ms.
2. Terminology:
   • V_{OPR MIN} = Minimum Operational Voltage level that ensures device functionality and specified performance in , Recommended Operating Conditions.
   • V_OFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.
   • Ramp Down = transition time from V_{OPR MIN} to V_OFF and is slew rate independent.
3. General timing diagram items:
   • Grey shaded areas show valid transition times for supplies between V_{OPR MIN} and V_OFF.
   • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
4. porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
5. vddshv[1-6] domains supplied by 3.3 V:
   • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100µs min, after porz is asserted low.
   • must not exceed vdds18v voltage level by more than 2V during ramp down, until vdds18v drops below V_OFF (0.6 V).
6. vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
7. vdd_dspeve, vdd, vdds_ddr[1-3], vdda_* domains can all start to ramp down in any order after 100 µs low assertion of porz.
8. vdds_ddr* domains:
   • can remain at V_{OPR MIN} or a level greater than vdds18v during ramp down.
   • elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.
9. vdda_* domains:
   • can start to ramp down before or concurrently with vdds18v.
   • must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below V_OFF (0.6 V).
10. vdds18v domain should maintain a minimum level of 1.62 V (V_NOM – 10%) until vdd_dspeve and vdd start to ramp down.