JAJSE41G June   2016  – March 2019 TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2 改訂履歴
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Digital-to-Analog Converter (SD_DAC)
      4. 4.4.4  Embedded 8 channel Analog-To-Digital Converter (ADC)
      5. 4.4.5  Camera Control
      6. 4.4.6  Camera Parallel Interface (CPI)
      7. 4.4.7  Imaging Subsystem (ISS)
      8. 4.4.8  External Memory Interface (EMIF)
      9. 4.4.9  General-Purpose Memory Controller (GPMC)
      10. 4.4.10 Timers
      11. 4.4.11 Inter-Integrated Circuit Interface (I2C)
      12. 4.4.12 Universal Asynchronous Receiver Transmitter (UART)
      13. 4.4.13 Multichannel Serial Peripheral Interface (McSPI)
      14. 4.4.14 Quad Serial Peripheral Interface (QSPI)
      15. 4.4.15 Multichannel Audio Serial Port (McASP)
      16. 4.4.16 Controller Area Network Interface (DCAN and MCAN)
      17. 4.4.17 Ethernet Interface (GMAC_SW)
      18. 4.4.18 SDIO Controller
      19. 4.4.19 General-Purpose Interface (GPIO)
      20. 4.4.20 Pulse Width Modulation (PWM) Interface
      21. 4.4.21 Test Interfaces
      22. 4.4.22 System and Miscellaneous
        1. 4.4.22.1 Sysboot
        2. 4.4.22.2 Power, Reset and Clock Management (PRCM)
        3. 4.4.22.3 Enhanced Direct Memory Access (EDMA)
        4. 4.4.22.4 Interrupt Controllers (INTC)
      23. 4.4.23 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
      1. 5.3 Power On Hour (POH) Limits
        1. 5.3.1 Power on Hour (POH) Limits
        2. 5.3.2 Recommended Operating Conditions
    3. 5.4 Operating Performance Points
      1. 5.4.1 AVS Requirements
      2. 5.4.2 Voltage And Core Clock Specifications
      3. 5.4.3 Maximum Supported Frequency
    4. 5.5 Power Consumption Summary
    5. 5.6 Electrical Characteristics
      1. 5.6.1 LVCMOS DDR DC Electrical Characteristics
      2. 5.6.2 Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. 5.6.3 IQ1833 Buffers DC Electrical Characteristics
      4. 5.6.4 IHHV1833 Buffers DC Electrical Characteristics
      5. 5.6.5 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. 5.6.6 LVCMOS CSI2 DC Electrical Characteristics
      7. 5.6.7 Dual Voltage LVCMOS DC Electrical Characteristics
    6. 5.7 Thermal Characteristics
      1. 5.7.1 Package Thermal Characteristics
    7. 5.8 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RC On-die Oscillator Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
        1. 6.2.2.1 DPLL and DLL Noise Isolation
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8 V and 3.3 V Signal Transition Levels
        2. 7.3.1.2 1.8 V and 3.3 V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Video Input Ports (VIP)
    6. 7.6  Display Subsystem – Video Output Ports
    7. 7.7  Imaging Subsystem (ISS)
    8. 7.8  External Memory Interface (EMIF)
    9. 7.9  General-Purpose Memory Controller (GPMC)
      1. 7.9.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.9.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.9.3 GPMC/NAND Flash Interface Asynchronous Timing
    10. 7.10 General-Purpose Timers
      1. 7.10.1 GP Timer Features
    11. 7.11 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-15 Timing Requirements for I2C Input Timings
      2. Table 7-16 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    12. 7.12 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-17 Timing Requirements for UART
      2. Table 7-18 Switching Characteristics Over Recommended Operating Conditions for UART
    13. 7.13 Multichannel Serial Peripheral Interface (McSPI)
    14. 7.14 Quad Serial Peripheral Interface (QSPI)
    15. 7.15 Multichannel Audio Serial Port (McASP)
      1. Table 7-26 Timing Requirements for McASP1
      2. Table 7-27 Timing Requirements for McASP2
      3. Table 7-28 Timing Requirements for McASP3
      4. Table 7-29 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-30 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-31 Switching Characteristics Over Recommended Operating Conditions for McASP3
    16. 7.16 Controller Area Network Interface (DCAN and MCAN)
      1. 7.16.1     DCAN
      2. 7.16.2     MCAN
      3. Table 7-34 Timing Requirements for CAN Receive
      4. Table 7-35 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
    17. 7.17 Ethernet Interface (GMAC_SW)
      1. 7.17.1 GMAC MDIO Interface Timings
      2. 7.17.2 GMAC RGMII Timings
        1. Table 7-39 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-40 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-41 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-42 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    18. 7.18 SDIO Controller
      1. 7.18.1 MMC, SD Default Speed
      2. 7.18.2 MMC, SD High Speed
      3. 7.18.3 MMC, SD and SDIO SDR12 Mode
      4. 7.18.4 MMC, SD SDR25 Mode
    19. 7.19 General-Purpose Interface (GPIO)
    20. 7.20 Test Interfaces
      1. 7.20.1 JTAG Electrical Data/Timing
        1. Table 7-53 Timing Requirements for IEEE 1149.1 JTAG
        2. Table 7-54 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
        3. Table 7-55 Timing Requirements for IEEE 1149.1 JTAG With RTCK
        4. Table 7-56 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.20.2 Trace Port Interface Unit (TPIU)
        1. 7.20.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1  Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2  Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 8.2.5.3 ESD Protection System Design Consideration
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3  Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd_dspeve Example Analysis
    4. 8.4  Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
        1. 8.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 8.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 8.5  Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 CSI2 Board Design and Routing Guidelines
        1. 8.5.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 8.5.2.1.1 General Guidelines
          2. 8.5.2.1.2 Length Mismatch Guidelines
            1. 8.5.2.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 8.5.2.1.3 Frequency-domain Specification Guidelines
    6. 8.6  Clock Routing Guidelines
      1. 8.6.1 Oscillator Ground Connection
    7. 8.7  LPDDR2 Board Design and Layout Guidelines
      1. 8.7.1 LPDDR2 Board Designs
      2. 8.7.2 LPDDR2 Device Configurations
      3. 8.7.3 LPDDR2 Interface
        1. 8.7.3.1 LPDDR2 Interface Schematic
        2. 8.7.3.2 Compatible JEDEC LPDDR2 Devices
        3. 8.7.3.3 LPDDR2 PCB Stackup
        4. 8.7.3.4 LPDDR2 Placement
        5. 8.7.3.5 LPDDR2 Keepout Region
        6. 8.7.3.6 LPDDR2 Net Classes
        7. 8.7.3.7 LPDDR2 Signal Termination
        8. 8.7.3.8 LPDDR2 DDR_VREF Routing
      4. 8.7.4 Routing Specification
        1. 8.7.4.1 DQS[x] and DQ[x] Routing Specification
        2. 8.7.4.2 CK and ADDR_CTRL Routing Specification
    8. 8.8  DDR2 Board Design and Layout Guidelines
      1. 8.8.1 DDR2 General Board Layout Guidelines
      2. 8.8.2 DDR2 Board Design and Layout Guidelines
        1. 8.8.2.1 Board Designs
        2. 8.8.2.2 DDR2 Interface
          1. 8.8.2.2.1  DDR2 Interface Schematic
          2. 8.8.2.2.2  Compatible JEDEC DDR2 Devices
          3. 8.8.2.2.3  PCB Stackup
          4. 8.8.2.2.4  Placement
          5. 8.8.2.2.5  DDR2 Keepout Region
          6. 8.8.2.2.6  Bulk Bypass Capacitors
          7. 8.8.2.2.7  High-Speed Bypass Capacitors
          8. 8.8.2.2.8  Net Classes
          9. 8.8.2.2.9  DDR2 Signal Termination
          10. 8.8.2.2.10 VREF Routing
        3. 8.8.2.3 DDR2 CK and ADDR_CTRL Routing
    9. 8.9  DDR3 Board Design and Layout Guidelines
      1. 8.9.1 DDR3 General Board Layout Guidelines
      2. 8.9.2 DDR3 Board Design and Layout Guidelines
        1. 8.9.2.1  Board Designs
        2. 8.9.2.2  DDR3 Device Combinations
        3. 8.9.2.3  DDR3 Interface Schematic
          1. 8.9.2.3.1 32-Bit DDR3 Interface
          2. 8.9.2.3.2 16-Bit DDR3 Interface
        4. 8.9.2.4  Compatible JEDEC DDR3 Devices
        5. 8.9.2.5  PCB Stackup
        6. 8.9.2.6  Placement
        7. 8.9.2.7  DDR3 Keepout Region
        8. 8.9.2.8  Bulk Bypass Capacitors
        9. 8.9.2.9  High-Speed Bypass Capacitors
          1. 8.9.2.9.1 Return Current Bypass Capacitors
        10. 8.9.2.10 Net Classes
        11. 8.9.2.11 DDR3 Signal Termination
        12. 8.9.2.12 VTT
        13. 8.9.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.9.2.13.1 Three DDR3 Devices
            1. 8.9.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 8.9.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 8.9.2.13.2 Two DDR3 Devices
            1. 8.9.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.9.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.9.2.13.3 One DDR3 Device
            1. 8.9.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.9.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 8.9.2.14 Data Topologies and Routing Definition
          1. 8.9.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.9.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 8.9.2.15 Routing Specification
          1. 8.9.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 8.9.2.15.2 DQS and DQ Routing Specification
    10. 8.10 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 商標
    7. 9.7 静電気放電に関する注意事項
    8. 9.8 Export Control Notice
    9. 9.9 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

8.9.2.9 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power, and processor/DDR ground connections. Table 8-41 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:

  1. Fit as many HS bypass capacitors as possible.
  2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
  3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
  4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible.
  5. Minimize via sharing. Note the limites on via sharing shown in Table 8-41.

Table 8-41 High-Speed Bypass Capacitors

NO. PARAMETER MIN TYP MAX UNIT
1 HS bypass capacitor package size(1) 0201 0402 10 Mils
2 Distance, HS bypass capacitor to processor being bypassed(2)(3)(4) 400 Mils
3 Processor HS bypass capacitor count per vdds_ddrx rail(12) See Table 8-3 and (11) Devices
4 Processor HS bypass capacitor total capacitance per vdds_ddrx rail(12) See Table 8-3 and (11) μF
5 Number of connection vias for each device power/ground ball(5) Vias
6 Trace length from device power/ground ball to connection via(2) 35 70 Mils
7 Distance, HS bypass capacitor to DDR device being bypassed(6) 150 Mils
8 DDR3 device HS bypass capacitor count(7) 12 Devices
9 DDR3 device HS bypass capacitor total capacitance(7) 0.85 μF
10 Number of connection vias for each HS capacitor(8)(9) 2 Vias
11 Trace length from bypass capacitor connect to connection via(2)(9) 35 100 Mils
12 Number of connection vias for each DDR3 device power/ground ball(10) 1 Vias
13 Trace length from DDR3 device power/ground ball to connection via(2)(8) 35 60 Mils
  1. LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
  2. Closer/shorter is better.
  3. Measured from the nearest processor power/ground ball to the center of the capacitor package.
  4. Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls, between the DDR interfaces on the package.
  5. See the Via Channel™ escape for the processor package.
  6. Measured from the DDR3 device power/ground ball to the center of the capacitor package.
  7. Per DDR3 device.
  8. An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board.
  9. An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
  10. Up to a total of two pairs of DDR power/ground balls may share a via.
  11. The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
  12. For more information, see Section 8.3, Core Power Domains.