5.4.2 Voltage And Core Clock Specifications
Table 5-3 shows the recommended OPP per voltage domain.
Table 5-3 Voltage Domains Operating Performance Points
DOMAIN |
CONDITION |
OPP_NOM |
OPP_OD |
OPP_HIGH/OPP_PLUS(6) |
MIN (2) |
NOM (1) |
MAX (2) |
MIN (2) |
NOM (1) |
MAX (2) |
MIN (2) |
NOM (1) |
MAX DC (3) |
MAX (2) |
VD_CORE (V) |
BOOT (Before AVS is enabled) (4) |
1.02 |
1.06 |
1.11 |
Not Applicable |
Not Applicable |
After AVS is enabled (4) |
AVS Voltage (5) – 3.5% |
AVS Voltage (5) |
1.20 |
Not Applicable |
Not Applicable |
VD_DSPEVE (V) |
BOOT (Before AVS is enabled) (4) |
1.02 |
1.06 |
1.11 |
Not Applicable |
Not Applicable |
After AVS is enabled (4) |
AVS Voltage (5) – 3.5% |
AVS Voltage (5) |
1.11 |
AVS Voltage (5) – 3.5% |
AVS Voltage (5) |
AVS Voltage (5) + 5% |
AVS Voltage (5) – 3.5% |
AVS Voltage (5) |
AVS Voltage (5) + 2% |
AVS Voltage (5) + 5% |
- In a typical implementation, the power supply should target the NOM voltage.
- The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
- The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH (Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
- For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
- The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM. The power supply should be adjustable over the following ranges for each required OPP:
- OPP_NOM: 0.85V - 1.06V
- OPP_OD: 0.94V - 1.15V
- OPP_HIGH: 1.05V - 1.25V
- OPP_PLUS: 1.05V - 1.25V
The AVS Voltages will be within the above specified ranges.
- The required PRCM and DCC software configuration sequence for OPP_PLUS (DSP 1 GHz or EVE 900 MHz) is different than other OPPs. For details refer to TDA3x SoC for Advanced Driver Assistance Systems (ADAS) Silicon Revision 2.0, 1.0A, 1.0, section titled "PRCM Software Configuration for OPP_PLUS".
Table 5-4 describes the standard processor clocks speed characteristics vs OPP of the device.
Table 5-4 Supported OPP vs Max Frequency(1)(2)
DESCRIPTION |
OPP_NOM |
OPP_OD |
OPP_HIGH |
OPP_PLUS |
MAX FREQ. (MHz) |
MAX FREQ. (MHz) |
MAX FREQ. (MHz) |
MAX FREQ. (MHz) |
VD_DSPEVE |
|
DSP_CLK |
500 |
709 |
745 |
1000 |
EVE_FCLK |
500 |
667 |
667 |
900 |
VD_CORE |
|
CORE_IPU1_CLK |
212.8 |
N/A |
N/A |
N/A |
ISS |
212.8 |
N/A |
N/A |
N/A |
L3_CLK |
266 |
N/A |
N/A |
N/A |
DDR3 / DDR3L |
532 (DDR-1066) |
N/A |
N/A |
N/A |
DDR2 |
400 (DDR-800) |
N/A |
N/A |
N/A |
LPPDR2 |
333 (DDR-667) |
N/A |
N/A |
N/A |
ADC |
20 |
N/A |
N/A |
N/A |
- N/A in this table stands for Not Applicable.
- Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-1).