JAJSQ14A february   2023  – august 2023 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
      2.      12
    3. 6.3 Signal Descriptions
      1.      14
      2. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
          1.        22
          2.        23
          3.        24
          4.        25
      4. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
          1.        28
        2. 6.3.3.2 WKUP Domain
          1.        30
      5. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
          1.        33
          2.        34
          3.        35
          4.        36
          5.        37
          6.        38
          7.        39
        2. 6.3.4.2 MCU Domain
          1.        41
          2.        42
        3. 6.3.4.3 WKUP Domain
          1.        44
      6. 6.3.5  I3C
        1. 6.3.5.1 MCU Domain
          1.        47
      7. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
          1.        50
          2.        51
          3.        52
          4.        53
          5.        54
          6.        55
          7.        56
          8.        57
          9.        58
          10.        59
          11.        60
          12.        61
          13.        62
          14.        63
          15.        64
          16.        65
          17.        66
          18.        67
        2. 6.3.6.2 MCU Domain
          1.        69
          2.        70
      8. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
          1.        73
          2.        74
          3.        75
          4.        76
          5.        77
          6.        78
          7.        79
        2. 6.3.7.2 MCU Domain
          1.        81
          2.        82
      9. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
          1.        85
          2.        86
          3.        87
          4.        88
          5.        89
          6.        90
          7.        91
          8.        92
          9.        93
          10.        94
        2. 6.3.8.2 MCU Domain
          1.        96
        3. 6.3.8.3 WKUP Domain
          1.        98
      10. 6.3.9  MDIO
        1. 6.3.9.1 MAIN Domain
          1.        101
          2.        102
        2. 6.3.9.2 MCU Domain
          1.        104
      11. 6.3.10 UFS
        1. 6.3.10.1 MAIN Domain
          1.        107
      12. 6.3.11 CPSW2G
        1. 6.3.11.1 MAIN Domain
          1.        110
        2. 6.3.11.2 MCU Domain
          1.        112
      13. 6.3.12 SGMII
        1. 6.3.12.1 MAIN Domain
          1.        115
      14. 6.3.13 ECAP
        1. 6.3.13.1 MAIN Domain
          1.        118
          2.        119
          3.        120
      15. 6.3.14 EQEP
        1. 6.3.14.1 MAIN Domain
          1.        123
          2.        124
          3.        125
      16. 6.3.15 EPWM
        1. 6.3.15.1 MAIN Domain
          1.        128
          2.        129
          3.        130
          4.        131
          5.        132
          6.        133
          7.        134
      17. 6.3.16 USB
        1. 6.3.16.1 MAIN Domain
          1.        137
      18. 6.3.17 Display Port
        1. 6.3.17.1 MAIN Domain
          1.        140
      19. 6.3.18 Hyperlink
        1. 6.3.18.1 MAIN Domain
          1.        143
          2.        144
          3.        145
      20. 6.3.19 PCIE
        1. 6.3.19.1 MAIN Domain
          1.        148
      21. 6.3.20 SERDES
        1. 6.3.20.1 MAIN Domain
          1.        151
          2.        152
          3.        153
          4.        154
      22. 6.3.21 DSI
        1. 6.3.21.1 MAIN Domain
          1.        157
          2.        158
      23. 6.3.22 CSI
        1. 6.3.22.1 MAIN Domain
          1.        161
          2.        162
          3.        163
      24. 6.3.23 MCASP
        1. 6.3.23.1 MAIN Domain
          1.        166
          2.        167
          3.        168
          4.        169
          5.        170
      25. 6.3.24 DMTIMER
        1. 6.3.24.1 MAIN Domain
          1.        173
        2. 6.3.24.2 MCU Domain
          1.        175
      26. 6.3.25 CPTS
        1. 6.3.25.1 MAIN Domain
          1.        178
        2. 6.3.25.2 MCU Domain
          1.        180
      27. 6.3.26 DSS
        1. 6.3.26.1 MAIN Domain
          1.        183
      28. 6.3.27 GPMC
        1. 6.3.27.1 MAIN Domain
          1.        186
      29. 6.3.28 MMC
        1. 6.3.28.1 MAIN Domain
          1.        189
          2.        190
      30. 6.3.29 OSPI
        1. 6.3.29.1 MCU Domain
          1.        193
          2.        194
      31. 6.3.30 Hyperbus
        1. 6.3.30.1 MCU Domain
          1.        197
      32. 6.3.31 Emulation and Debug
        1. 6.3.31.1 MAIN Domain
          1.        200
          2.        201
      33. 6.3.32 System and Miscellaneous
        1. 6.3.32.1 Boot Mode configuration
          1.        204
        2. 6.3.32.2 Clock
          1.        206
          2.        207
        3. 6.3.32.3 System
          1.        209
          2.        210
        4. 6.3.32.4 EFUSE
          1.        212
        5. 6.3.32.5 VMON
          1.        214
      34. 6.3.33 Power
        1.       216
    4. 6.4 Pin Connectivity Requirements
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On-Hour (POH) Limits
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 7.6.7  ADC12B Electrical Characteristics
      8. 7.6.8  LVCMOS Electrical Characteristics
      9. 7.6.9  USB2PHY Electrical Characteristics
      10. 7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 7.6.11 UFS M-PHY Electrical Characteristics
      12. 7.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 7.6.13 DDR0 Electrical Characteristics
    7. 7.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8  Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics for ALY Package
    9. 7.9  Temperature Sensor Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Module and Peripheral Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  CPSW2G
          1. 7.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.2.2 CPSW2G RMII Timings
            1. 7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.2.3 CPSW2G RGMII Timings
            1. 7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 7.10.5.3  CSI-2
        4. 7.10.5.4  DDRSS
        5. 7.10.5.5  DSS
        6. 7.10.5.6  eCAP
          1. 7.10.5.6.1 Timing Requirements for eCAP
          2. 7.10.5.6.2 Switching Characteristics for eCAP
        7. 7.10.5.7  EPWM
          1. 7.10.5.7.1 Timing Requirements for eHRPWM
          2. 7.10.5.7.2 Switching Characteristics for eHRPWM
        8. 7.10.5.8  eQEP
          1. 7.10.5.8.1 Timing Requirements for eQEP
          2. 7.10.5.8.2 Switching Characteristics for eQEP
        9. 7.10.5.9  GPIO
          1. 7.10.5.9.1 GPIO Timing Requirements
          2. 7.10.5.9.2 GPIO Switching Characteristics
        10. 7.10.5.10 GPMC
          1. 7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 7.10.5.10.4 GPMC0 IOSET
        11. 7.10.5.11 HyperBus
          1. 7.10.5.11.1 Timing Requirements for HyperBus
          2. 7.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 7.10.5.12 I2C
        13. 7.10.5.13 I3C
        14. 7.10.5.14 MCAN
        15. 7.10.5.15 MCASP
        16. 7.10.5.16 MCSPI
          1. 7.10.5.16.1 MCSPI — Controller Mode
          2. 7.10.5.16.2 MCSPI — Peripheral Mode
        17. 7.10.5.17 MMCSD
          1. 7.10.5.17.1 MMC0 - eMMC Interface
            1. 7.10.5.17.1.1 Legacy SDR Mode
            2. 7.10.5.17.1.2 High Speed SDR Mode
            3. 7.10.5.17.1.3 High Speed DDR Mode
            4. 7.10.5.17.1.4 HS200 Mode
            5. 7.10.5.17.1.5 HS400 Mode
          2. 7.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.17.2.1 Default Speed Mode
            2. 7.10.5.17.2.2 High Speed Mode
            3. 7.10.5.17.2.3 UHS–I SDR12 Mode
            4. 7.10.5.17.2.4 UHS–I SDR25 Mode
            5. 7.10.5.17.2.5 UHS–I SDR50 Mode
            6. 7.10.5.17.2.6 UHS–I DDR50 Mode
            7. 7.10.5.17.2.7 UHS–I SDR104 Mode
        18. 7.10.5.18 CPTS
          1. 7.10.5.18.1 CPTS Timing Requirements
          2. 7.10.5.18.2 CPTS Switching Characteristics
        19. 7.10.5.19 OSPI
          1. 7.10.5.19.1 OSPI0 PHY Mode
            1. 7.10.5.19.1.1 OSPI With Data Training
              1. 7.10.5.19.1.1.1 OSPI Switching Characteristics – Data Training
            2. 7.10.5.19.1.2 OSPI Without Data Training
              1. 7.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 7.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 7.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 7.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 7.10.5.19.2 OSPI0 Tap Mode
            1. 7.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 7.10.5.20 OLDI
          1. 7.10.5.20.1 OLDI Switching Characteristics
        21. 7.10.5.21 PCIE
        22. 7.10.5.22 Timers
          1. 7.10.5.22.1 Timing Requirements for Timers
          2. 7.10.5.22.2 Switching Characteristics for Timers
        23. 7.10.5.23 UART
          1. 7.10.5.23.1 Timing Requirements for UART
          2. 7.10.5.23.2 UART Switching Characteristics
        24. 7.10.5.24 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
      3. 8.2.3 DSP C71x
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 GPU
      2. 8.3.2 VPAC
      3. 8.3.3 DMPAC
    4. 8.4 Other Subsystems
      1. 8.4.1 MSMC
      2. 8.4.2 NAVSS
        1. 8.4.2.1 NAVSS0
        2. 8.4.2.2 MCU_NAVSS
      3. 8.4.3 PDMA Controller
      4. 8.4.4 Power Supply
      5. 8.4.5 Peripherals
        1. 8.4.5.1  ADC
        2. 8.4.5.2  ATL
        3. 8.4.5.3  CSI
          1. 8.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 8.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 8.4.5.4  CPSW2G
        5. 8.4.5.5  CPSW9G
        6. 8.4.5.6  DCC
        7. 8.4.5.7  DDRSS
        8. 8.4.5.8  DSS
          1. 8.4.5.8.1 DSI
          2. 8.4.5.8.2 eDP
        9. 8.4.5.9  VPFE
        10. 8.4.5.10 eCAP
        11. 8.4.5.11 EPWM
        12. 8.4.5.12 ELM
        13. 8.4.5.13 ESM
        14. 8.4.5.14 eQEP
        15. 8.4.5.15 GPIO
        16. 8.4.5.16 GPMC
        17. 8.4.5.17 Hyperbus
        18. 8.4.5.18 I2C
        19. 8.4.5.19 I3C
        20. 8.4.5.20 MCAN
        21. 8.4.5.21 MCASP
        22. 8.4.5.22 MCRC Controller
        23. 8.4.5.23 MCSPI
        24. 8.4.5.24 MMC/SD
        25. 8.4.5.25 OSPI
        26. 8.4.5.26 PCIE
        27. 8.4.5.27 SerDes
        28. 8.4.5.28 WWDT
        29. 8.4.5.29 Timers
        30. 8.4.5.30 UART
        31. 8.4.5.31 USB
        32. 8.4.5.32 UFS
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.1.1.1 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG and EMU
      4. 9.1.4 Reset
      5. 9.1.5 Unused Pins
      6. 9.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal Flash devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ALY|1414
サーマルパッド・メカニカル・データ
発注情報

Table 6-123 Power Supply Signal Descriptions
SIGNAL NAME [1]PIN TYPE [2]DESCRIPTION [3]ALY PIN [4]
CAP_VDDS0 (1)CAPExternal Capacitor ConnectionV29
CAP_VDDS0_MCU (1)CAPExternal Capacitor ConnectionL27
CAP_VDDS1_MCU (1)CAPExternal Capacitor ConnectionL25
CAP_VDDS2 (1)CAPExternal Capacitor ConnectionT29
CAP_VDDS2_MCU (1)CAPExternal Capacitor ConnectionL26
CAP_VDDS5 (1)CAPExternal Capacitor ConnectionP29
VDDAR_COREPWRCore RAM SupplyAB27, AC24, AF15, AF18, AF21, AG11, AG28, T25
VDDAR_CPUPWRCPU RAM SupplyAB13, AC16, AC18, AC20, AE12, M21, N23, T15, U20, W14, W21, Y11, Y19
VDDAR_MCUPWRMCU RAM SupplyM27, N24
VDDA_0P8_DSITXPWRAnalog Supply for DSITXAJ24
VDDA_0P8_DSITX_CPWRDSITX Clock SupplyAJ25
VDDA_0P8_UFSPWRUFS 0.8V SupplyAH11
VDDA_0P8_USBPWRUSB 0.8V SupplyAK20
VDDA_0P8_CSIRX2PWRAnalog Supply for CSIRXAJ28
VDDA_0P8_CSIRX0_1PWRAnalog Supply for CSIRXAJ26, AK26
VDDA_0P8_DLL_MMC0PWRMMC DLL Analog SupplyAE9
VDDA_0P8_PLL_DDR0PWRDDR de-skew PLL Analog SupplyU11
VDDA_0P8_PLL_DDR1PWRDDR de-skew PLL Analog SupplyM14
VDDA_0P8_PLL_DDR2PWRDDR de-skew PLL Analog SupplyN11
VDDA_0P8_PLL_DDR3PWRDDR de-skew PLL Analog SupplyM18
VDDA_0P8_SERDES2PWRSERDES 0.8V SupplyAJ20, AJ21
VDDA_0P8_SERDES4PWRSERDES 0.8V SupplyAJ17, AJ18
VDDA_0P8_SERDES0_1PWRSERDES 0.8V SupplyAJ12, AJ15, AK13, AK14
VDDA_0P8_SERDES_C2PWRSERDES 0.8V Clock SupplyAG21, AH20
VDDA_0P8_SERDES_C4PWRSERDES 0.8V Clock SupplyAG17, AH18
VDDA_0P8_SERDES_C0_1PWRSERDES 0.8V Clock SupplyAH12, AH13, AH15, AH16
VDDA_1P8_DSITXPWRAnalog Supply for DSITXAH24, AH25
VDDA_1P8_UFSPWRUFS 1.8V SupplyAJ10
VDDA_1P8_USBPWRUSB 1.8V SupplyAK21
VDDA_1P8_CSIRX2PWRAnalog Supply for CSIRXAH29, AJ29
VDDA_1P8_CSIRX0_1PWRAnalog Supply for CSIRXAH27, AH28
VDDA_1P8_SERDES2PWRSERDES 1.8V SupplyAH21
VDDA_1P8_SERDES4PWRSERDES 1.8V SupplyAH17
VDDA_1P8_SERDES0_1PWRSERDES 1.8V SupplyAJ13, AJ14
VDDA_1P8_SERDES2_4PWRSERDES 1.8V SupplyAJ23
VDDA_3P3_USBPWRUSB 3.3V SupplyAJ19
VDDA_ADC0PWRADC0 Analog SupplyM31
VDDA_ADC1PWRADC1 Analog SupplyN30
VDDA_MCU_PLLGRP0PWRAnalog Supply for MCU PLL Group 0M28
VDDA_MCU_TEMPPWRAnalog Supply for MCU temperature sensorM26
VDDA_OSC1PWRHFOSC1 SupplyN29
VDDA_PLLGRP0PWRAnalog Supply for MAIN PLL Group 0AA27
VDDA_PLLGRP1PWRAnalog Supply for MAIN PLL Group 1Y28
VDDA_PLLGRP2PWRAnalog Supply for MAIN PLL Group 2AG13
VDDA_PLLGRP5PWRAnalog Supply for MAIN PLL Group 5V14
VDDA_PLLGRP6PWRAnalog Supply for MAIN PLL Group 6R21
VDDA_PLLGRP7PWRAnalog Supply for MAIN PLL Group 7P12
VDDA_PLLGRP8PWRAnalog Supply for MAIN PLL Group 8P15
VDDA_PLLGRP9PWRAnalog Supply for MAIN PLL Group 9Y26
VDDA_PLLGRP10PWRAnalog Supply for MAIN PLL Group 10AG23
VDDA_PLLGRP12PWRAnalog Supply for MAIN PLL Group 12AA23
VDDA_PLLGRP13PWRAnalog Supply for MAIN PLL Group 13AB26
VDDA_POR_WKUPPWRWKUP domain Analog SupplyN28
VDDA_TEMP0PWRAnalog Supply for temperature sensor 0Y27
VDDA_TEMP1PWRAnalog Supply for temperature sensor 1M12
VDDA_TEMP2PWRAnalog Supply for temperature sensor 2W23
VDDA_TEMP3PWRAnalog Supply for temperature sensor 3AE13
VDDA_TEMP4PWRAnalog Supply for temperature sensor 4AD18
VDDA_WKUPPWROscillator Supply for WKUP domainK31, L32
VDDSHV0PWRIO Power SupplyV30, V32, W31
VDDSHV0_MCUPWRIO Power SupplyH29, J28, K29
VDDSHV1_MCUPWRIO Power SupplyH25, J24, K25
VDDSHV2PWRIO Power SupplyT30, T32, U31
VDDSHV2_MCUPWRIO Power SupplyH27, J26, K27
VDDSHV5PWRIO Power SupplyP31, R30, R31
VDDS_DDRPWRDDR PHY IO SupplyA31, AK1, B1, H11, H13, H15, H17, H19, H9, J10, J12, J14, J16, J18, J8, K11, K13, K15, K17, K19, K9, L10, L12, L14, L16, L18, M9, N10, N8, P9, R10, R8, T9, U10, U8
VDDS_DDR_C0PWRIO Power Supply for DDR ClockT10
VDDS_DDR_C1PWRIO Power Supply for DDR ClockL15
VDDS_DDR_C2PWRIO Power Supply for DDR ClockM10
VDDS_DDR_C3PWRIO Power Supply for DDR ClockL17
VDDS_MMC0PWRMMC0 PHY IO SupplyAF9, AG10, AG8, AH9
VDD_COREPWRMAIN domain core SupplyAA24, AA26, AA28, AA30, AB25, AB29, AB31, AC26, AC28, AC30, AD25, AD27, AD29, AD31, AE24, AE26, AE28, AE30, AE32, AF13, AF17, AF19, AF23, AF25, AF27, AF29, AF31, AG12, AG14, AG16, AG18, AG20, AG22, AG24, AG26, AG30, AG32, AH31, AJ30, M11, M13, M15, M17, M19, N12, N16, N18, P11, P17, P19, R12, R14, R16, R18, R24, R26, R28, T11, T13, T27, U12, U24, U26, U28, V25, V27, W24, W26, W28, W30, W32, Y25, Y29, Y31
VDD_CPUPWRCPU core SupplyAA10, AA12, AA14, AA20, AA22, AA8, AB11, AB19, AB21, AB23, AB9, AC10, AC12, AC14, AC22, AD11, AD13, AD15, AD17, AD19, AD21, AD23, AD9, AE10, AE14, AE16, AE18, AE20, AE22, AF11, H21, H23, J20, J22, K21, K23, L20, L22, N20, N22, P21, R20, R22, T17, T19, T21, T23, U14, U22, V11, V13, V19, V21, V23, V9, W10, W12, W20, W22, W8, Y13, Y21, Y23, Y9
VDD_MCUPWRMCU core SupplyL24, M23, M25, N26, P23, P25, P27
VDD_MCU_WAKE1PWRCore Supply for MCU daisy chainL28
VDD_WAKE0PWRCore Supply for MAIN domain daisy chainU29
VSSGNDGroundA1, A10, A12, A15, A2, A20, A23, A25, A28, A34, A37, A5, A7, AA11, AA13, AA19, AA2, AA21, AA25, AA29, AA34, AA36, AA38, AA5, AA9, AB1, AB10, AB12, AB14, AB20, AB22, AB24, AB28, AB30, AB32, AB33, AB35, AB37, AB5, AB8, AC11, AC13, AC15, AC17, AC19, AC2, AC21, AC23, AC25, AC27, AC29, AC31, AC6, AC9, AD1, AD10, AD12, AD14, AD16, AD20, AD22, AD24, AD26, AD28, AD30, AD32, AD35, AD4, AD8, AE11, AE15, AE17, AE19, AE2, AE21, AE23, AE25, AE27, AE29, AE31, AE5, AF10, AF12, AF14, AF16, AF20, AF22, AF24, AF26, AF28, AF3, AF30, AF32, AF6, AF8, AG1, AG15, AG19, AG25, AG27, AG29, AG31, AG4, AG7, AG9, AH10, AH14, AH19, AH2, AH22, AH23, AH26, AH30, AH32, AH35, AH5, AH8, AJ11, AJ16, AJ22, AJ27, AJ3, AJ31, AJ6, AJ8, AJ9, AK10, AK11, AK12, AK15, AK16, AK17, AK18, AK19, AK22, AK23, AK24, AK25, AK27, AK28, AK30, AK32, AL1, AL10, AL12, AL13, AL14, AL15, AL16, AL17, AL18, AL19, AL21, AL26, AL29, AL31, AL4, AM11, AM13, AM15, AM18, AM20, AM23, AM25, AM27, AM3, AM30, AM32, AM38, AM6, AN1, AN10, AN12, AN14, AN16, AN19, AN22, AN25, AN28, AN31, AN34, AN4, AN7, AP12, AP15, AP18, AP21, AP24, AP27, AP3, AP30, AP33, AP36, AP6, AP9, AR1, AR10, AR13, AR16, AR19, AR22, AR25, AR28, AR31, AR34, AR37, AR4, AR7, AT12, AT15, AT18, AT21, AT24, AT27, AT3, AT30, AT33, AT36, AT6, AT9, AU1, AU10, AU13, AU16, AU19, AU22, AU25, AU28, AU31, AU34, AU37, AU38, AU4, AU7, AV1, AV11, AV14, AV17, AV2, AV20, AV23, AV26, AV29, AV32, AV35, AV5, AV8, B11, B13, B16, B19, B22, B24, B26, B29, B31, B38, B6, B9, C14, C17, C18, C2, C21, C27, C30, C4, C8, D10, D15, D20, D23, D28, D3, D35, D6, D7, E12, E13, E16, E19, E2, E22, E25, E26, E29, E31, E5, E9, F1, F11, F14, F17, F21, F24, F27, F30, F4, F7, F8, G15, G18, G20, G28, G3, G6, H10, H16, H18, H2, H20, H22, H24, H26, H28, H30, H31, H5, H7, H8, J1, J11, J13, J15, J17, J19, J21, J23, J25, J27, J29, J32, J4, J9, K10, K12, K14, K16, K18, K2, K20, K22, K24, K26, K6, K8, L1, L11, L13, L19, L21, L23, L31, L5, L9, M16, M2, M20, M22, M24, M29, M30, M32, M5, M8, N15, N17, N19, N21, N25, N3, N31, N32, N38, N6, N9, P1, P10, P16, P18, P20, P22, P24, P26, P30, P32, P35, P37, P4, P7, P8, R11, R13, R15, R17, R19, R2, R23, R25, R27, R32, R34, R36, R38, R5, R9, T12, T14, T16, T18, T20, T22, T24, T26, T28, T3, T31, T33, T35, T37, T6, T8, U13, U19, U21, U23, U25, U27, U3, U30, U32, U34, U36, U38, U6, U9, V10, V12, V2, V20, V22, V24, V26, V28, V31, V33, V35, V37, V5, V8, W1, W11, W13, W19, W25, W27, W29, W34, W36, W38, W4, W7, W9, Y10, Y12, Y14, Y20, Y22, Y24, Y3, Y30, Y32, Y33, Y35, Y37, Y6, Y8
(1) This pin must always be connected via a 1-μF ±10% capacitor to VSS.