JAJSQ14A february   2023  – august 2023 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
      2.      12
    3. 6.3 Signal Descriptions
      1.      14
      2. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
          1.        22
          2.        23
          3.        24
          4.        25
      4. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
          1.        28
        2. 6.3.3.2 WKUP Domain
          1.        30
      5. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
          1.        33
          2.        34
          3.        35
          4.        36
          5.        37
          6.        38
          7.        39
        2. 6.3.4.2 MCU Domain
          1.        41
          2.        42
        3. 6.3.4.3 WKUP Domain
          1.        44
      6. 6.3.5  I3C
        1. 6.3.5.1 MCU Domain
          1.        47
      7. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
          1.        50
          2.        51
          3.        52
          4.        53
          5.        54
          6.        55
          7.        56
          8.        57
          9.        58
          10.        59
          11.        60
          12.        61
          13.        62
          14.        63
          15.        64
          16.        65
          17.        66
          18.        67
        2. 6.3.6.2 MCU Domain
          1.        69
          2.        70
      8. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
          1.        73
          2.        74
          3.        75
          4.        76
          5.        77
          6.        78
          7.        79
        2. 6.3.7.2 MCU Domain
          1.        81
          2.        82
      9. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
          1.        85
          2.        86
          3.        87
          4.        88
          5.        89
          6.        90
          7.        91
          8.        92
          9.        93
          10.        94
        2. 6.3.8.2 MCU Domain
          1.        96
        3. 6.3.8.3 WKUP Domain
          1.        98
      10. 6.3.9  MDIO
        1. 6.3.9.1 MAIN Domain
          1.        101
          2.        102
        2. 6.3.9.2 MCU Domain
          1.        104
      11. 6.3.10 UFS
        1. 6.3.10.1 MAIN Domain
          1.        107
      12. 6.3.11 CPSW2G
        1. 6.3.11.1 MAIN Domain
          1.        110
        2. 6.3.11.2 MCU Domain
          1.        112
      13. 6.3.12 SGMII
        1. 6.3.12.1 MAIN Domain
          1.        115
      14. 6.3.13 ECAP
        1. 6.3.13.1 MAIN Domain
          1.        118
          2.        119
          3.        120
      15. 6.3.14 EQEP
        1. 6.3.14.1 MAIN Domain
          1.        123
          2.        124
          3.        125
      16. 6.3.15 EPWM
        1. 6.3.15.1 MAIN Domain
          1.        128
          2.        129
          3.        130
          4.        131
          5.        132
          6.        133
          7.        134
      17. 6.3.16 USB
        1. 6.3.16.1 MAIN Domain
          1.        137
      18. 6.3.17 Display Port
        1. 6.3.17.1 MAIN Domain
          1.        140
      19. 6.3.18 Hyperlink
        1. 6.3.18.1 MAIN Domain
          1.        143
          2.        144
          3.        145
      20. 6.3.19 PCIE
        1. 6.3.19.1 MAIN Domain
          1.        148
      21. 6.3.20 SERDES
        1. 6.3.20.1 MAIN Domain
          1.        151
          2.        152
          3.        153
          4.        154
      22. 6.3.21 DSI
        1. 6.3.21.1 MAIN Domain
          1.        157
          2.        158
      23. 6.3.22 CSI
        1. 6.3.22.1 MAIN Domain
          1.        161
          2.        162
          3.        163
      24. 6.3.23 MCASP
        1. 6.3.23.1 MAIN Domain
          1.        166
          2.        167
          3.        168
          4.        169
          5.        170
      25. 6.3.24 DMTIMER
        1. 6.3.24.1 MAIN Domain
          1.        173
        2. 6.3.24.2 MCU Domain
          1.        175
      26. 6.3.25 CPTS
        1. 6.3.25.1 MAIN Domain
          1.        178
        2. 6.3.25.2 MCU Domain
          1.        180
      27. 6.3.26 DSS
        1. 6.3.26.1 MAIN Domain
          1.        183
      28. 6.3.27 GPMC
        1. 6.3.27.1 MAIN Domain
          1.        186
      29. 6.3.28 MMC
        1. 6.3.28.1 MAIN Domain
          1.        189
          2.        190
      30. 6.3.29 OSPI
        1. 6.3.29.1 MCU Domain
          1.        193
          2.        194
      31. 6.3.30 Hyperbus
        1. 6.3.30.1 MCU Domain
          1.        197
      32. 6.3.31 Emulation and Debug
        1. 6.3.31.1 MAIN Domain
          1.        200
          2.        201
      33. 6.3.32 System and Miscellaneous
        1. 6.3.32.1 Boot Mode configuration
          1.        204
        2. 6.3.32.2 Clock
          1.        206
          2.        207
        3. 6.3.32.3 System
          1.        209
          2.        210
        4. 6.3.32.4 EFUSE
          1.        212
        5. 6.3.32.5 VMON
          1.        214
      34. 6.3.33 Power
        1.       216
    4. 6.4 Pin Connectivity Requirements
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On-Hour (POH) Limits
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 7.6.7  ADC12B Electrical Characteristics
      8. 7.6.8  LVCMOS Electrical Characteristics
      9. 7.6.9  USB2PHY Electrical Characteristics
      10. 7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 7.6.11 UFS M-PHY Electrical Characteristics
      12. 7.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 7.6.13 DDR0 Electrical Characteristics
    7. 7.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8  Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics for ALY Package
    9. 7.9  Temperature Sensor Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing
        6. 7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Module and Peripheral Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  CPSW2G
          1. 7.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.2.2 CPSW2G RMII Timings
            1. 7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.2.3 CPSW2G RGMII Timings
            1. 7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 7.10.5.3  CSI-2
        4. 7.10.5.4  DDRSS
        5. 7.10.5.5  DSS
        6. 7.10.5.6  eCAP
          1. 7.10.5.6.1 Timing Requirements for eCAP
          2. 7.10.5.6.2 Switching Characteristics for eCAP
        7. 7.10.5.7  EPWM
          1. 7.10.5.7.1 Timing Requirements for eHRPWM
          2. 7.10.5.7.2 Switching Characteristics for eHRPWM
        8. 7.10.5.8  eQEP
          1. 7.10.5.8.1 Timing Requirements for eQEP
          2. 7.10.5.8.2 Switching Characteristics for eQEP
        9. 7.10.5.9  GPIO
          1. 7.10.5.9.1 GPIO Timing Requirements
          2. 7.10.5.9.2 GPIO Switching Characteristics
        10. 7.10.5.10 GPMC
          1. 7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 7.10.5.10.4 GPMC0 IOSET
        11. 7.10.5.11 HyperBus
          1. 7.10.5.11.1 Timing Requirements for HyperBus
          2. 7.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 7.10.5.12 I2C
        13. 7.10.5.13 I3C
        14. 7.10.5.14 MCAN
        15. 7.10.5.15 MCASP
        16. 7.10.5.16 MCSPI
          1. 7.10.5.16.1 MCSPI — Controller Mode
          2. 7.10.5.16.2 MCSPI — Peripheral Mode
        17. 7.10.5.17 MMCSD
          1. 7.10.5.17.1 MMC0 - eMMC Interface
            1. 7.10.5.17.1.1 Legacy SDR Mode
            2. 7.10.5.17.1.2 High Speed SDR Mode
            3. 7.10.5.17.1.3 High Speed DDR Mode
            4. 7.10.5.17.1.4 HS200 Mode
            5. 7.10.5.17.1.5 HS400 Mode
          2. 7.10.5.17.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.17.2.1 Default Speed Mode
            2. 7.10.5.17.2.2 High Speed Mode
            3. 7.10.5.17.2.3 UHS–I SDR12 Mode
            4. 7.10.5.17.2.4 UHS–I SDR25 Mode
            5. 7.10.5.17.2.5 UHS–I SDR50 Mode
            6. 7.10.5.17.2.6 UHS–I DDR50 Mode
            7. 7.10.5.17.2.7 UHS–I SDR104 Mode
        18. 7.10.5.18 CPTS
          1. 7.10.5.18.1 CPTS Timing Requirements
          2. 7.10.5.18.2 CPTS Switching Characteristics
        19. 7.10.5.19 OSPI
          1. 7.10.5.19.1 OSPI0 PHY Mode
            1. 7.10.5.19.1.1 OSPI With Data Training
              1. 7.10.5.19.1.1.1 OSPI Switching Characteristics – Data Training
            2. 7.10.5.19.1.2 OSPI Without Data Training
              1. 7.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 7.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 7.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 7.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 7.10.5.19.2 OSPI0 Tap Mode
            1. 7.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 7.10.5.20 OLDI
          1. 7.10.5.20.1 OLDI Switching Characteristics
        21. 7.10.5.21 PCIE
        22. 7.10.5.22 Timers
          1. 7.10.5.22.1 Timing Requirements for Timers
          2. 7.10.5.22.2 Switching Characteristics for Timers
        23. 7.10.5.23 UART
          1. 7.10.5.23.1 Timing Requirements for UART
          2. 7.10.5.23.2 UART Switching Characteristics
        24. 7.10.5.24 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
      3. 8.2.3 DSP C71x
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 GPU
      2. 8.3.2 VPAC
      3. 8.3.3 DMPAC
    4. 8.4 Other Subsystems
      1. 8.4.1 MSMC
      2. 8.4.2 NAVSS
        1. 8.4.2.1 NAVSS0
        2. 8.4.2.2 MCU_NAVSS
      3. 8.4.3 PDMA Controller
      4. 8.4.4 Power Supply
      5. 8.4.5 Peripherals
        1. 8.4.5.1  ADC
        2. 8.4.5.2  ATL
        3. 8.4.5.3  CSI
          1. 8.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 8.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 8.4.5.4  CPSW2G
        5. 8.4.5.5  CPSW9G
        6. 8.4.5.6  DCC
        7. 8.4.5.7  DDRSS
        8. 8.4.5.8  DSS
          1. 8.4.5.8.1 DSI
          2. 8.4.5.8.2 eDP
        9. 8.4.5.9  VPFE
        10. 8.4.5.10 eCAP
        11. 8.4.5.11 EPWM
        12. 8.4.5.12 ELM
        13. 8.4.5.13 ESM
        14. 8.4.5.14 eQEP
        15. 8.4.5.15 GPIO
        16. 8.4.5.16 GPMC
        17. 8.4.5.17 Hyperbus
        18. 8.4.5.18 I2C
        19. 8.4.5.19 I3C
        20. 8.4.5.20 MCAN
        21. 8.4.5.21 MCASP
        22. 8.4.5.22 MCRC Controller
        23. 8.4.5.23 MCSPI
        24. 8.4.5.24 MMC/SD
        25. 8.4.5.25 OSPI
        26. 8.4.5.26 PCIE
        27. 8.4.5.27 SerDes
        28. 8.4.5.28 WWDT
        29. 8.4.5.29 Timers
        30. 8.4.5.30 UART
        31. 8.4.5.31 USB
        32. 8.4.5.32 UFS
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.1.1.1 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG and EMU
      4. 9.1.4 Reset
      5. 9.1.5 Unused Pins
      6. 9.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal Flash devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ALY|1414
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from February 19, 2023 to August 18, 2023 (from Revision * (FEBRUARY 2023) to Revision A (AUGUST 2023))

  • グローバル：すべての OLDI/LVDS コンテンツを削除、このデバイス・スイートに該当なしGo
  • グローバル：3D グラフィックス処理ユニット (GPU) について、「BSX」、「BSX-64-4」、および「BXS-64-4」から「IMG BXS-4-64」に更新 / 変更Go
  • (パッケージ情報)：新しいコンテンツ標準に合わせて表を更新 / 変更Go
  • (機能ブロック図)：スーパーセット・デバイスを示すように画像を更新 / 変更し、新しい画像には適用できないため関連する脚注を削除 Go
  • (機能ブロック図)：ソフトウェア・ビルド・シートの注を追加Go
  • (Device Comparison): Merged table cells to show commonality/differences and to improve readability.Go
  • (Device Comparison): Added software build sheet noteGo
  • (Device Comparison): Changed MSMC sizeGo
  • (Device Comparison): Modified restrictions on SERDES muxing for PCIe and SGMII to allow flexible mapping for 4-port SGMII and 1x4L/2x2l PCIe.Go
  • (Device Comparison): Added notes to clarify LPDDR instance usage for a) software compatibility with 27 mm package, and b) requirements for using fewer than 4 DDR instancesGo
  • (Device Comparison): Added notes to clarify that SERDES2 is not available on a 27mm package variant of this SoC.Go
  • (Pin Attributes): Added "VDDA_0P8_DLL_MMC0" power supply to the MMC0 IO Power GroupGo
  • (DDRSS0 Signal Descriptions): Added "DDRSS incremental order" footnoteGo
  • (DDRSS1 Signal Descriptions): Added "DDRSS incremental order" footnoteGo
  • (DDRSS2 Signal Descriptions): Added "DDRSS incremental order" footnoteGo
  • (DDRSS2 Signal Descriptions): Added DDRSS2, DDRSS3, and SERDES2 availability footnoteGo
  • (DDRSS3 Signal Descriptions): Added "DDRSS incremental order" footnoteGo
  • (DDRSS3 Signal Descriptions): Added DDRSS2, DDRSS3, and SERDES2 availability footnoteGo
  • (SERDES2 Signal Descriptions): Added DDRSS2, DDRSS3, and SERDES2 availability footnoteGo
  • (Pin Connectivity Requirements) Updated ADC AIN recommendation to allow the tie-off of signals directly to ground.Go
  • (Pin Connectivity Requirements): Added requirement for DDR interfaces to be used in incrementing orderGo
  • (Recommended Operating Conditions): Added clarification to the "… supply inputs" footnote, specifically for VDD_CORE, VDD_MCU, and VDD_CPU domains plus, added cross-references to the MIN/MAX valuesGo
  • (Recommended Operating Conditions): Added vdda_* noise specificationGo
  • (USB VBUS Design Guidelines): Updated/Changed USB VBUS Detect Voltage Divider / Clamp Circuit figureGo