JAJSQ14A february 2023 – august 2023 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
ADVANCE INFORMATION
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
MODE | OSPI_PHY_CONFIGURATION_REG BIT FIELD | DELAY VALUE |
---|---|---|
All modes | PHY_CONFIG_TX_DLL_DELAY_FLD | 0x0 |
PHY_CONFIG_RX_DLL_DELAY_FLD | 0x0 |
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
O21 | tsu(D-LBCLK) | Setup time, D[i:0] valid before active LBCLK input (DQS) edge(1) | 1.8V, External Board Loopback | 0.6 | ns | |
3.3V, External Board Loopback | 0.9 | ns | ||||
O22 | th(LBCLK-D) | Hold time, D[i:0] valid after active LBCLK input (DQS) edge(1) | 1.8V, External Board Loopback | 1.7 | ns | |
3.3V, External Board Loopback | 2 | ns |