JAJSQ14A february 2023 – august 2023 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
ADVANCE INFORMATION
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Table 7-88, Figure 7-104, Table 7-89, and Figure 7-105 present timing requirements and switching characteristics for OSPI0 Tap DDR Mode.
NO. | MODE | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
O13 | tsu(D-CLK) | Setup time, OSPI0/1_D[7:0] valid before active OSPI0/1_CLK edge | No Loopback | (12.04 - (0.975T(1)R(3))) | ns | |
O14 | th(CLK-D) | Hold time, OSPI0/1_D[7:0] valid after active OSPI0/1_CLK edge | No Loopback | (1.84 + (0.975T(1)R(3))) | ns |
NO. | PARAMETER | MODE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
O1 | tc(CLK) | Cycle time, OSPI0/1_CLK | 40 | ns | ||
O2 | tw(CLKL) | Pulse duration, OSPI0/1_CLK low | ((0.475P(1)) - 0.3) | ns | ||
O3 | tw(CLKH) | Pulse duration, OSPI0/1_CLK high | ((0.475P(1)) - 0.3) | ns | ||
O4 | td(CSn-CLK) | Delay time, OSPI0/1_CSn[3:0] active edge to OSPI0/1_CLK rising edge | ((0.475P(1)) + ((0.975M(2)R(4)) - 1) | ((0.525P(1)) + (1.025M(2)R(4)) + 1) | ns | |
O5 | td(CLK-CSn) | Delay time, OSPI0/1_CLK rising edge to OSPI0/1_CSn[3:0] inactive edge | ((0.475P(1)) + (0.975N(3)R(4)) - 1) | ((0.525P(1)) + (1.025N(3)R(4)) + 1) | ns | |
O6 | td(CLK-D) | Delay time, OSPI0/1_CLK active edge to OSPI0/1_D[7:0] transition | (–17.94 + (0.975T(5)R(4))) | (–1.56 + (1.025T(5)R(4))) | ns |