JAJSQ14A february 2023 – august 2023 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1
ADVANCE INFORMATION
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NO.(2) | PARAMETER | DESCRIPTION | MODE(19) | MIN | MAX | MIN | MAX | UNIT |
---|---|---|---|---|---|---|---|---|
100 MHz(23) | 133 MHz(23) | |||||||
F0 | tc(clk) | Period, output clock GPMC_CLK(18) | div_by_1_mode; ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | 10 | 7.52 | ns | ||
F1 | tw(clkH) | Typical pulse duration, output clock GPMC_CLK high | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | 0.475*P(15)- 0.3 | 0.475*P(15)- 0.3 | ns | ||
F1 | tw(clkL) | Typical pulse duration, output clock GPMC_CLK low | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | 0.475*P(15)- 0.3 | 0.475*P(15)- 0.3 | ns | ||
F2 | td(clkH-csnV) | Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition(14) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 no extra_delay | F(6)- 2.2 | F+3.75 | F(6)- 2.2 | F(6)+ 3.75 | ns |
F3 | td(clkH-CSn[i]V) | Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid(14) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 no extra_delay | E(5)- 2.2 | E(5)+ 3.75 | E(5)- 2.2 | E(5)+ 3.75 | ns |
F4 | td(aV-clk) | Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | B(2)-2.3 | B(2)+4.5 | B(2)-2.3 | B(2)+4.5 | ns |
F5 | td(clkH-aIV) | Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | –2.3 | 4.5 | –2.3 | 4.5 | ns |
F6 | td(be[x]nV-clk) | Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | B(2)-2.3 | B(2)+1.9 | B(2)-2.3 | B(2)+1.9 | ns |
F7 | td(clkH-be[x]nIV) | Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(11) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | D(4)-2.3 | D(4)+1.9 | D(4)-2.3 | D(4)+1.9 | ns |
F7 | td(clkL-be[x]nIV) | Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | D(4)-2.3 | D(4)+1.9 | D(4)-2.3 | D(4)+1.9 | ns |
F7 | td(clkL-be[x]nIV). | Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(13) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | D(4)-2.3 | D(4)+1.9 | D(4)-2.3 | D(4)+1.9 | ns |
F8 | td(clkH-advn) | Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 no extra_delay | G(7)-2.3 | G(7)+4.5 | G(7)-2.3 | G(7)+4.5 | ns |
F9 | td(clkH-advnIV) | Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 no extra_delay | D(4)-2.3 | D(4)+4.5 | D(4)-2.3 | D(4)+4.5 | ns |
F10 | td(clkH-oen) | Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 no extra_delay | H(8)-2.3 | H(8)+3.5 | H(8)-2.3 | H(8)+3.5 | ns |
F11 | td(clkH-oenIV) | Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 no extra_delay | E(8)-2.3 | E(8)+3.5 | E(8)-2.3 | E(8)+ 3.5 | ns |
F14 | td(clkH-wen) | Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 no extra_delay | I(9)- 2.3 | I(9)+4.5 | I(9)- 2.3 | I(9)+4.5 | ns |
F15 | td(clkH-do) | Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(11) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | J(10)-2.3 | J(10)+2.7 | J(10)-2.3 | J(10)+2.7 | ns |
F15 | td(clkL-do) | Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | J(10)-2.3 | J(10)+2.7 | J(10)-2.3 | J(10)+2.7 | ns |
F15 | td(clkL-do). | Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(13) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | J(10)-2.3 | J(10)+2.7 | J(10)-2.3 | J(10)+2.7 | ns |
F17 | td(clkH-be[x]n) | Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(11) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | J(10)-2.3 | J(10)+1.9 | J(10)-2.3 | J(10)+1.9 | ns |
F17 | td(clkL-be[x]n) | Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | J(10)-2.3 | J(10)+1.9 | J(10)-2.3 | J(10)+1.9 | ns |
F17 | td(clkL-be[x]n). | Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(13) | div_by_1_mode ; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 | J(10)-2.3 | J(10)+1.9 | J(10)-2.3 | J(10)+1.9 | ns |
F18 | tw(csnV) | Pulse duration, output chip select GPMC_CSn[i] low(14) | Read | A(1) | A(1) | ns | ||
Write | A(1) | A(1) | ns | |||||
F19 | tw(be[x]nV) | Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low | Read | C(3) | C(3) | ns | ||
Write | C(3) | C(3) | ns | |||||
F20 | tw(advnV) | Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low | Read | K(16) | K(16) | ns | ||
Write | K(16) | K(16) | ns |