JAJSIF7 データシート

JAJSIF7K September 2021 – April 2024 TDA4VM , TDA4VM-Q1

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ALF|827

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6.6 Electrical Characteristics

Note:

The interfaces or signals described in Table 6-2through Table 6-9 correspond to the interfaces or signals available in multiplexing mode 0 (Primary Function).

All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions).

Table 6-2 I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics Over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
BALL NAMES in Mode 0: WKUP_I2C0_SDA, WKUP_I2C0_SCL, MCU_I2C0_SDA, MCU_I2C0_SCL, I2C0_SDA, I2C0_SCL, I2C1_SDA, I2C1_SCL, EXTINTN
BALL NUMBERS:H24 / J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18 H24/ J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18
1.8-V MODE
V_IL	Input low-level threshold			0.3 × VDDSHV⁽¹⁾	V
V_ILSS	Input low-level threshold steady state			0.3 × VDDSHV⁽¹⁾	V
V_IH	Input high-level threshold		0.7 × VDDSHV⁽¹⁾		V
V_IHSS	Input high-level threshold steady state		0.7 × VDDSHV⁽¹⁾		V
V_HYS	Input Hysteresis Voltage		0.1 × VDDSHV⁽¹⁾		mV
I_IN	Input Leakage Current	V_I = 1.8 V or 0 V		±10	µA
V_OL	Output low-level voltage			0.2 × VDDSHV⁽¹⁾	V
I_OL⁽²⁾	Low Level Output Current	V_OL(MAX)	6		mA
SR_I⁽⁴⁾	Input Slew Rate		18f⁽³⁾ or 1.8E+6		V/s
3.3-V MODE⁽⁵⁾
V_IL	Input low-level threshold			0.3 × VDDSHV⁽¹⁾	V
V_ILSS	Input low-level threshold steady state			0.25 × VDDSHV⁽¹⁾	V
V_IH	Input high-level threshold		0.7 × VDDSHV⁽¹⁾		V
V_IHSS	Input high-level threshold steady state		0.7 × VDDSHV⁽¹⁾		V
V_HYS	Input Hysteresis Voltage		0.05 × VDDSHV⁽¹⁾		mV
I_IN	Input Leakage Current	V_I = 3.3 V or 0 V		±10	µA
V_OL	Output low-level voltage			0.4⁽¹⁾	V
I_OL⁽²⁾	Low Level Output Current	V_OL(MAX)	6		mA
SR_I⁽⁴⁾	Input Slew Rate		33f⁽³⁾ or 3.3E+6	8E + 7	V/s

(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.

(2) The I_OL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified V_OL value. The value defined by this parameter should be considered the maximum current available to a system implementation which needs to maintain the specified V_OL value for attached components.

(3) f = toggle frequency of the input signal in Hz.

(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value.

(5) I2C Hs-mode is not supported, when operating the IO in 3.3-V mode.

Table 6-3 Fail-Safe Reset (FS Reset) Electrical Characteristics Over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
BALL NAMES in Mode 0: MCU_PORz, PORz
BALL NUMBERS:H23 / J24
V_IL	Input low-level threshold			0.3 × VDDSHV⁽¹⁾	V
V_ILSS	Input low-level threshold steady state			0.3 × VDDSHV⁽¹⁾	V
V_IH	Input high-level threshold		0.7 × VDDSHV⁽¹⁾		V
V_IHSS	Input high-level threshold steady state		0.7 × VDDSHV⁽¹⁾		V
V_HYS	Input Hysteresis Voltage		200		mV
I_IN	Input Leakage Current	V_I = 1.8 V or 0 V		±10	µA

(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.

Table 6-4 HFOSC/LFOSC Electrical Characteristics Over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
HIGH FREQUENCY OSCILLATOR
BALL NAMES: WKUP_OSC0_XO, WKUP_OSC0_XI, OSC1_XO, OSC1_XI
BALL NUMBERS:M27 / M29 / P27 / P29
V_IH	Input high-level threshold		0.65 × VDDSHV⁽¹⁾			V
V_IL	Input low-level threshold				0.35 × VDDSHV⁽¹⁾	V
V_HYS	Input Hysteresis Voltage			49		mV
LOW FREQUENCY OSCILLATOR
BALL NAMES: WKUP_LFOSC0_XO, WKUP_LFOSC0_XI
BALL NUMBERS:N26 / N28
V_IH	Input high-level threshold		0.65 × VDDA_WKUP⁽¹⁾			V
V_IL	Input low-level threshold				0.35 × VDDA_WKUP⁽¹⁾	V
V_HYS	Input Hysteresis Voltage	Active Mode		85		mV
V_HYS	Input Hysteresis Voltage	Bypass Mode		324		mV

(1) VDDSHV stands for corresponding power supply. For WKUP_OSC0, the corresponding power supply is VDDA_WKUP. For OSC1_XI, the corresponding power supply is VDDS_OSC1.

Table 6-5 eMMCPHY Electrical Characteristics Over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
BALL NAMES in Mode 0: MMC0_DAT[7:0], MMC0_CALPAD, MMC0_CMD, MMC0_DS, MMC0_CLK
BALL NUMBERS:AG2 / AH1 / AG3 / AF4 / AE5 / AF3 / AG1 / AF2 / AE1 / AE3 / AE4 / AF1
V_IL	Input low-level threshold				0.35 × VDDSHV⁽¹⁾	V
V_ILSS	Input low-level threshold steady state				0.20	V
V_IH	Input high-level threshold		0.65 × VDDSHV⁽¹⁾			V
V_IHSS	Input high-level threshold steady state		1.4			V
I_IN	Input Leakage Current	V_I = 1.8 V or 0 V			±10	µA
I_OZ	Tri-state Output Leakage Current	V_O = 1.8 V or 0 V			±10	µA
R_PU	Pull-up Resistor		15	20	25	kΩ
R_PD	Pull-down Resistor		15	20	25	kΩ
V_OL	Output low-level voltage				0.30	V
V_OH	Output high-level voltage		VDDSHV - 0.30⁽¹⁾			V
I_OL	Low Level Output Current	V_OL(MAX)	2			mA
I_OH	High Level Output Current	V_OH(MAX)	2			mA
SR_I	Input Slew Rate		5E + 8			V/s

(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.

Table 6-6 SDIO Electrical Characteristics Over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
BALL NAMES in Mode 0: MMC1_CLK, MMC1_CMD, MMC1_DAT[3:0], MMC2_CLK, MMC2_CMD, MMC2_DAT[3:0]
BALL NUMBERS:P25 / R29 / R24 / P24 / R25 / R26 / T26 / T25 / T24 / T27 / T29 / T28
1.8-V MODE
V_IL	Input low-level threshold				0.58	V
V_ILSS	Input low-level threshold steady state				0.58	V
V_IH	Input high-level threshold		1.27			V
V_IHSS	Input high-level threshold steady state		1.7			V
V_HYS	Input Hysteresis Voltage		150			mV
I_IN	Input Leakage Current	V_I = 1.8 V or 0 V			±10	µA
R_PU	Pull-up Resistor		40	50	60	kΩ
R_PD	Pull-down Resistor		40	50	60	kΩ
V_OL	Output low-level voltage				0.45	V
V_OH	Output high-level voltage		VDDSHV- 0.45⁽¹⁾			V
I_OL	Low Level Output Current	V_OL(MAX)	4			mA
I_OH	High Level Output Current	V_OH(MAX)	4			mA
SR_I⁽³⁾	Input Slew Rate		18f⁽²⁾ or 1.8E+6			V/s
3.3-V Mode
V_IL	Input low-level threshold				0.25 × VDDSHV⁽¹⁾	V
V_ILSS	Input low-level threshold steady state				0.15 × VDDSHV⁽¹⁾	V
V_IH	Input high-level threshold		0.625 × VDDSHV⁽¹⁾			V
V_IHSS	Input high-level threshold steady state		0.625 × VDDSHV⁽¹⁾			V
V_HYS	Input Hysteresis Voltage		150			mV
I_IN	Input Leakage Current	V_I = 1.8 V or 0 V			±10	µA
R_PU	Pull-up Resistor		40	50	60	kΩ
R_PD	Pull-down Resistor		40	50	60	kΩ
V_OL	Output low-level voltage				0.125 × VDDSHV⁽¹⁾	V
V_OH	Output high-level voltage		0.75 × VDDSHV⁽¹⁾			V
I_OL	Low Level Output Current	V_OL(MAX)	6			mA
I_OH	High Level Output Current	V_OH(MAX)	10			mA
SR_I⁽³⁾	Input Slew Rate		33f⁽²⁾ or 3.3E+6			V/s

(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.

(2) f = toggle frequency of the input signal in Hz.

(3) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value.

CSI-2/DSI D-PHY Electrical Characteristics

Note:

CSI-2/DSI (D-PHY) interfaces are compliant with MIPI D-PHY specifications v1.2 dated August 1, 2014, including ECNs and Errata as applicable.

Table 6-7 ADC12B Electrical Characteristics Over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0], MCU_ADC1_AIN[7:0]
BALL NUMBERS:K24 / K25 / K26 / K27 / K28 / K29 / L24 / L25 / L26 / L27 / L28 / L29 / M24 / M25 / N23 / N24
Analog Input
V_{MCU_ADC0/1_AIN[7:0]}	Full-scale Input Range		VSS		VDDA_ADC0/1	V
DNL	Differential Non-Linearity		-1	0.5	4	LSB
INL	Integral Non-Linearity			±1	±4	LSB
LSB_GAIN-ERROR	Gain Error			±2		LSB
LSB_OFFSET-ERROR	Offset Error			±2		LSB
C_IN	Input Sampling Capacitance			5.5		pF
SNR	Signal-to-Noise Ratio	Input Signal: 200 kHz sine wave at -0.5 dB Full Scale		70		dB
THD	Total Harmonic Distortion	Input Signal: 200 kHz sine wave at -0.5 dB Full Scale		73		dB
SFDR	Spurious Free Dynamic Range	Input Signal: 200 kHz sine wave at -0.5 dB Full Scale		76		dB
SNR_(PLUS)	Signal-to-Noise Plus Distortion	Input Signal: 200 kHz sine wave at -0.5 dB Full Scale		69		dB
R_{MCU_ADC0/1_AIN[0:7]}	Input Impedance of MCU_ADC0/1_AIN[7:0]	f = input frequency		[1/((65.97 × 10^–-12) × f_{SMPL_CLK})]		Ω
I_IN	Input Leakage	MCU_ADC0/1_AIN[7:0] = VSS			-10	μA
I_IN	Input Leakage	MCU_ADC0/1_AIN[7:0] = VDDA_ADC0/1			24	μA
Sampling Dynamics
F_{SMPL_CLK}	SMPL_CLK Frequency			60		MHz
t_C	Conversion Time			13		ADC0/1 SMPL_CLK Cycles
t_ACQ	Acquisition time		2		257	ADC0/1 SMPL_CLK Cycles
T_R	Sampling Rate	ADC0/1 SMPL_CLK = 60 MHz		4		MSPS
CCISO	Channel to Channel Isolation			100		dB
General Purpose Input Mode⁽¹⁾
V_IL	Input low-level threshold				0.35 × VDDA_ADC0/1	V
V_ILSS	Input high-level threshold steady state				0.35 × VDDA_ADC0/1	V
V_IH	Input high-level threshold		0.65 × VDDA_ADC0/1			V
V_IHSS	Input high-level threshold steady state		0.65 × VDDA_ADC0/1			V
V_HYS	Input Hysteresis Voltage		200			mV
I_IN	Input Leakage Current	V_I = 1.8 V or 0 V			6	µA

(1) MCU_ADC0/1 can be configured to operate in General Purpose Input mode, where all MCU_ADC0/1_AIN[7:0] inputs are globally enabled to operate as digital inputs via the ADC0/1_CTRL register (gpi_mode_en = 1).

Table 6-8 MLB LVCMOS Electrical Characteristics Only GPIO mode supported. Over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BALL NAMES in Mode 0: MLB0_MLBSN, MLB0_MLBDP, MLB0_MLBSP, MLB0_MLBCP, MLB0_MLBDN, MLB0_MLBCN
BALL NUMBERS:AC1 / AC3 / AD1 / AD2 / AD3 / AE2
V_IL	Input Low Voltage				0.3 × VDD⁽¹⁾	V
V_ILSS	Input Low Voltage Steady State				0.3 × VDD⁽¹⁾	V
V_IH	Input High Voltage		0.7 × VDD⁽¹⁾			V
V_IHSS	Input High Voltage Steady State		0.75 × VDD⁽¹⁾			V
V_HYS	Input Hysteresis Voltage		80			mV
I_IN	Input Leakage Current	V_I = 1.8 V or 0 V			±10	µA
R_PD	Pull-down Resistor		20	53	130	kΩ
V_OL	Output Low Voltage				0.2	V
V_OH	Output High Voltage		VDD⁽¹⁾ - 0.2			V
I_OL	Low Level Output Current	V_OL(MAX)	6			mA
I_OH	High Level Output Current	V_OH(MIN)	6			mA
SR_I	Input Slew Rate⁽²⁾	f_op > 100 MHz	1			V/ns
SR_I	Input Slew Rate⁽²⁾	f_op < 1 MHz	10			V/ns

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.

(2) Slew rate may be further limited, reference Section 6.9 for actual slew rate during operation.

Table 6-9 LVCMOS Electrical Characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER⁽¹⁾		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BALL NAMES: ALL other IOs
BALL NUMBERS: ALL other IOs
1.8-V MODE
V_IL	Input Low Voltage				0.35 × VDD⁽¹⁾	V
V_ILSS	Input Low Voltage Steady State				0.3 × VDD⁽¹⁾	V
V_IH	Input High Voltage		0.65 × VDD⁽¹⁾			V
V_IHSS	Input High Voltage Steady State		0.85 × VDD⁽¹⁾			V
V_HYS	Input Hysteresis Voltage		150			mV
I_IN	Input Leakage Current.	V_I = 1.8 V or 0 V			±10	µA
R_PU	Pull-up Resistor		15	22	30	kΩ
R_PD	Pull-down Resistor		15	22	30	kΩ
V_OL	Output Low Voltage				0.45	V
V_OH	Output High Voltage		VDD⁽¹⁾ - 0.45			V
I_OL⁽²⁾	Low Level Output Current	V_OL(MAX)	3			mA
I_OH⁽²⁾	High Level Output Current	V_OH(MIN)	3			mA
SR_I⁽⁴⁾	Input Slew Rate		18f⁽³⁾ or 1.8E+6			V/s
3.3-V MODE
V_IL	Input Low Voltage				0.8	V
V_ILSS	Input Low Voltage Steady State				0.6	V
V_IH	Input High Voltage		2.0			V
V_IHSS	Input High Voltage Steady State		2.0			V
V_HYS	Input Hysteresis Voltage		150			mV
I_IN	Input Leakage Current.	V_I = 3.3 V or 0 V			±10	µA
R_PD	Pull-down Resistor		15	22	30	kΩ
V_OL	Output Low Voltage				0.4	V
V_OH	Output High Voltage		2.4			V
I_OL⁽²⁾	Low Level Output Current	V_OL(MAX)	5			mA
I_OH⁽²⁾	High Level Output Current	V_OH(MIN)	6			mA
SR_I⁽⁴⁾	Input Slew Rate		33f⁽³⁾ or 3.3E+6			V/s

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.

(2) The I_OL and I_OH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able to maintain the specified V_OL and V_OH values. Values defined by these parameters should be considered the maximum current available to a system implementation which needs to maintain the specified V_OL and V_OH values for attached components.

(3) f = toggle frequency of the input signal in Hz.

USB2PHY Electrical Characteristics

Note:

USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable.

SerDes 4-L-PHY/2-L-PHY Electrical Characteristics

Note:

The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base Specification Revision 4.0, September 27, 2017.

This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal termination enabled, as described by parameter V_{REFCLK_TERM} in Table 6-10, 4-L-PHY SERDES REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled before applying a reference clock signal that exceeds the limits defined by V_{REFCLK_TERM}. External termination should always be enabled on the source side.

Table 6-10 4-L-PHY SERDES REFCLK Electrical Characteristics Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
BALL NAMES in Mode 0: SERDES4_REFCLK_P, SERDES4_REFCLK_N
BALL NUMBERS:E8 / E7
V_{REFCLK_TERM}	Single ended voltage threshold at the reference clock pin when internal termination is enabled			400	mV
R_TERM	Internal termination	40	50	62.5	Ω

Note:

The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26, 2013.

Note:

The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3 Clause 70.

Note:

The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.

Note:

The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.

This Device imposes an additional limit on the 2-L-PHY SERDES REFCLK, as described by parameters V_IDTH and V_IDTL in Table 6-11, 2-L-PHY SERDES REFCLK Electrical Characteristics.

Table 6-11 2-L-PHY SERDES REFCLK Electrical Characteristics Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
BALL NAMES in Mode 0: PCIE_REFCLK[3:0]P, PCIE_REFCLK[3:0]N
BALL NUMBERS:AE9 / AD10 / AE11 / AD12 / AE14 / AD15 / AE17 / AD16
V_IDTH	Input Differential high-level threshold		200	mV
V_IDTL	Input Differential low-level threshold	–200		mV

UFS M-PHY Electrical Characteristics

Note:

The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1, February 17, 2014.

eDP/DP AUX-PHY Electrical Characteristics

Note:

The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v 1.4 February 23, 2016.

Note:

The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort (eDP) Standard v1.4b October 23, 2015.

DDR0 Electrical Characteristics

Note:

The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.