4 Device Comparison

Table 4-1 shows the features of the SoC.

Note: To understand what device features are currently supported by TI Software Development Kits (SDKs), see the DRA829 and TDA4VM Software Build Sheet (PROCESSOR-SDK-J721E).

Table 4-1 Device Comparison

FEATURES⁽⁷⁾	REFERENCE NAME	TDA4VM88	TDA4VM67	TDA4VM21
Features
PROCESSORS AND ACCELERATORS
Speed Grades		T	L	E
Arm Cortex-A72 Microprocessor Subsystem	Arm A72	Dual Core	Dual Core	Dual Core
Arm Cortex-R5F	Arm R5F	Hexa Core	Hexa Core	Quad Core⁽⁹⁾
Arm Cortex-R5F	Lockstep	Optional⁽¹⁾	Optional⁽¹⁾	Optional⁽¹⁾
Device Management Security Controller	DMSC	Yes	Yes	Yes
C7x Floating Point, Vector DSP	C7x DSP	Yes	Yes	Yes
Deep Learning Accelerator	MMA	Yes	Yes	Yes
Two C66x Floating Point DSP	C66x DSP	Dual Core	Dual Core	Single Core
Graphics Accelerator 3D GPU PowerVR Rogue 8XE GE8430	GPU	Yes	Yes	Yes
Depth and Motion Processing Accelerators	DMPAC	Yes	Yes	No
Vision Processing Accelerators	VPAC	Yes	Yes	Yes
Security Accelerators	SA	Yes	Yes	Yes
Video Encoder / Decoder	VENC/ VDEC	Yes	Yes	Yes
SAFETY AND SECURITY
Safety Targeted	Safety	Optional⁽¹⁾	Optional⁽¹⁾	Optional⁽¹⁾
Device Security	Security	Optional⁽²⁾	Optional⁽²⁾	Optional⁽²⁾
AEC-Q100 Qualified	Q1	Optional⁽³⁾	Optional⁽³⁾	Optional⁽³⁾
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain	OCSRAM	512KB SRAM	512KB SRAM	512KB SRAM
On-Chip Shared Memory (RAM) in MCU Domain	MCU_MSRAM	1MB SRAM	1MB SRAM	1MB SRAM
Multicore Shared Memory Controller	MSMC	8MB (On-Chip SRAM with ECC)	8MB (On-Chip SRAM with ECC)	8MB (On-Chip SRAM with ECC)
LPDDR4 DDR Subsystem	DDRSS	Up to 8GB (32-bit data) with inline ECC	Up to 8GB (32-bit data) with inline ECC	Up to 8GB (32-bit data) with inline ECC
LPDDR4 DDR Subsystem	SECDED	7-Bit	7-Bit	7-Bit
General-Purpose Memory Controller	GPMC	Up to 1GB with ECC	Up to 1GB with ECC	Up to 1GB with ECC
PERIPHERALS
Display Subsystem	DSS	Yes	Yes	Yes
Modular Controller Area Network Interface with Full CAN-FD Support	MCAN	16	16	16
General-Purpose I/O	GPIO	Up to 226	Up to 226	Up to 226
Inter-Integrated Circuit Interface	I2C	10	10	10
Improved Inter-Integrated Circuit Interface	I3C	3	3	3
Analog-to-Digital Converter	ADC	2	2	2
Capture Subsystem with Camera Serial Interface (CSI2)	CSI2.0 4L RX	2	2	2
Capture Subsystem with Camera Serial Interface (CSI2)	CSI2.0 4L TX	1	1	1
Multichannel Serial Peripheral Interface	MCSPI	11	11	11
Multichannel Audio Serial Port	MCASP0	16 Serializers	16 Serializers	16 Serializers
	MCASP1	12 Serializers	12 Serializers	12 Serializers
	MCASP2	6 Serializers	6 Serializers	6 Serializers
	MCASP3	4 Serializers	4 Serializers	4 Serializers
	MCASP4	4 Serializers	4 Serializers	4 Serializers
	MCASP5	4 Serializers	4 Serializers	4 Serializers
	MCASP6	4 Serializers	4 Serializers	4 Serializers
	MCASP7	4 Serializers	4 Serializers	4 Serializers
	MCASP8	4 Serializers	4 Serializers	4 Serializers
	MCASP9	4 Serializers	4 Serializers	4 Serializers
	MCASP10	8 Serializers	8 Serializers	8 Serializers
	MCASP11	8 Serializers	8 Serializers	8 Serializers
MultiMedia Card/ Secure Digital Interface	MMCSD0	eMMC (8-bits)	eMMC (8-bits)	eMMC (8-bits)
	MMCSD1	SD/SDIO (4-bits)	SD/SDIO (4-bits)	SD/SDIO (4-bits)
	MMCSD2	SD/SDIO (4-bits)	SD/SDIO (4-bits)	SD/SDIO (4-bits)
Universal Flash Storage	UFS 2L	Yes (2 Lanes)	Yes (2 Lanes)	Yes (2 Lanes)
Flash Subsystem (FSS)	OSPI0	8-bits⁽⁶⁾	8-bits⁽⁶⁾	8-bits⁽⁶⁾
	OSPI1^⁽⁸⁾	4-bits	4-bits	4-bits
	HyperBus	Yes⁽⁶⁾	Yes⁽⁶⁾	Yes⁽⁶⁾
4x PCI Express Port with Integrated PHY	PCIE0	Up to Two Lanes⁽⁴⁾	Up to Two Lanes⁽⁴⁾	Up to Two Lanes⁽⁴⁾
	PCIE1	Up to Two Lanes⁽⁴⁾	Up to Two Lanes⁽⁴⁾	Up to Two Lanes⁽⁴⁾
	PCIE2	Up to Two Lanes⁽⁴⁾	Up to Two Lanes⁽⁴⁾	Up to Two Lanes⁽⁴⁾
	PCIE3	Up to Two Lanes⁽⁴⁾	Up to Two Lanes⁽⁴⁾	Up to Two Lanes⁽⁴⁾
2x Programmable Real-Time Unit Subsystem and TSN Communication Subsystem (Ethernet Subsystem)	PRU_ICSSG0	No	No	No
	PRU_ICSSG1	No	No	No
Gigabit Ethernet Interface	CPSW2G	RMII or RGMII	RMII or RGMII	RMII or RGMII
Gigabit Ethernet Interface	CPSW9G	8 × RMII 8 × RGMII 8 × SGMII⁽⁴⁾	4 × RMII 4 × RGMII 4 × SGMII⁽⁴⁾⁽⁵⁾	2 × RMII 2 × RGMII 2 × SGMII⁽⁴⁾⁽⁵⁾
General-Purpose Timers	TIMER	30	30	30
Enhanced High Resolution Pulse-Width Modulator Module	eHRPWM	6	6	6
Enhanced Capture Module	eCAP	3	3	3
Enhanced Quadrature Encoder Pulse Module	eQEP	3	3	3
Universal Asynchronous Receiver and Transmitter	UART	12	12	12
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY	USB0	Yes⁽⁴⁾	Yes⁽⁴⁾	Yes⁽⁴⁾
	USB1	Yes⁽⁴⁾	Yes⁽⁴⁾	Yes⁽⁴⁾

(1) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the Device Type (Y) identifier in the Table 9-1, Nomenclature Description table.

(2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as indicated by the Device Type (Y) identifier in the Table 9-1, Nomenclature Description table..

(3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Table 9-1, Nomenclature Description table.

(4) DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes.

(5) Devices that support 4x RMII, 4x RGMII, 4x SGMII
Allowed instances and pins:

RMII1/RGMII1/SGMII1
RMII2/RGMII2/SGMII2
RMII3/RGMII3/SGMII3
RMII4/RGMII4/SGMII4

Devices that support 2x RMII, 2x RGMII, 2x SGMII
Allowed instances and pins:

RMII1/RGMII1/SGMII1
RMII2/RGMII2/SGMII2

(6) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.

(7) Software should constrain the features used to match the intended production device.

(8) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.

(9) The Quad Core R5F device provides support for a dual core RF5 in the MCU domain (MCU_R5FSS) and a dual core R5F in the Main domain (R5FSS0).