JAJSIF7K September   2021  – April 2024 TDA4VM , TDA4VM-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
    1. 3.1 機能ブロック図
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  DDRSS
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  GPIO
        1. 5.3.3.1 MAIN Domain
        2. 5.3.3.2 WKUP Domain
      4. 5.3.4  I2C
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 MCU Domain
        3. 5.3.4.3 WKUP Domain
      5. 5.3.5  I3C
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  MCAN
        1. 5.3.6.1 MAIN Domain
        2. 5.3.6.2 MCU Domain
      7. 5.3.7  MCSPI
        1. 5.3.7.1 MAIN Domain
        2. 5.3.7.2 MCU Domain
      8. 5.3.8  UART
        1. 5.3.8.1 MAIN Domain
        2. 5.3.8.2 MCU Domain
        3. 5.3.8.3 WKUP Domain
      9. 5.3.9  MDIO
        1. 5.3.9.1 MCU Domain
      10. 5.3.10 CPSW2G
        1. 5.3.10.1 MCU Domain
      11. 5.3.11 CPSW9G
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 ECAP
        1. 5.3.12.1 MAIN Domain
      13. 5.3.13 EQEP
        1. 5.3.13.1 MAIN Domain
      14. 5.3.14 EHRPWM
        1. 5.3.14.1 MAIN Domain
      15. 5.3.15 USB
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 SERDES
        1. 5.3.16.1 MAIN Domain
      17. 5.3.17 OSPI
        1. 5.3.17.1 MCU Domain
      18. 5.3.18 Hyperbus
        1. 5.3.18.1 MCU Domain
      19. 5.3.19 GPMC
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 MMC
        1. 5.3.20.1 MAIN Domain
      21. 5.3.21 CPTS
        1. 5.3.21.1 MCU Domain
        2. 5.3.21.2 MAIN Domain
      22. 5.3.22 UFS
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 PRU_ICSSG [Currently Not Supported]
        1. 5.3.23.1 MAIN Domain
      24. 5.3.24 MCASP
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 DSS
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 DP
        1. 5.3.26.1 MAIN Domain
      27. 5.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 5.3.27.1 MAIN Domain
      28. 5.3.28 DSI_TX
        1. 5.3.28.1 MAIN Domain
      29. 5.3.29 VPFE
        1. 5.3.29.1 MAIN Domain
      30. 5.3.30 DMTIMER
        1. 5.3.30.1 MAIN Domain
        2. 5.3.30.2 MCU Domain
      31. 5.3.31 Emulation and Debug
        1. 5.3.31.1 MAIN Domain
      32. 5.3.32 System and Miscellaneous
        1. 5.3.32.1 Boot Mode Configuration
          1. 5.3.32.1.1 MAIN Domain
          2. 5.3.32.1.2 MCU Domain
        2. 5.3.32.2 Clock
          1. 5.3.32.2.1 MAIN Domain
          2. 5.3.32.2.2 WKUP Domain
        3. 5.3.32.3 System
          1. 5.3.32.3.1 MAIN Domain
          2. 5.3.32.3.2 WKUP Domain
        4. 5.3.32.4 EFUSE
      33. 5.3.33 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On-Hour (POH) Limits
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
    6. 6.6 Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for ALF Package
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 6.9.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
        6. 6.9.2.6 Entry and Exit of MCU Only State
        7. 6.9.2.7 Entry and Exit of DDR Retention State
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input and Output Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.9.4.1.1.1 Load Capacitance
            2. 6.9.4.1.1.2 Shunt Capacitance
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.9.4.1.3.1 Load Capacitance
            2. 6.9.4.1.3.2 Shunt Capacitance
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 6.9.4.1.7 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Module and Peripheral Clocks Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  ATL
          1. 6.9.5.1.1 ATL_PCLK Timing Requirements
          2. 6.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.9.5.2  VPFE
        3. 6.9.5.3  CPSW2G
          1. 6.9.5.3.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.3.2 CPSW2G RMII Timings
            1. 6.9.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.9.5.3.3 CPSW2G RGMII Timings
            1. 6.9.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.9.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 6.9.5.4  CPSW9G
          1. 6.9.5.4.1 CPSW9G MDIO Interface Timings
          2. 6.9.5.4.2 CPSW9G RMII Timings
            1. 6.9.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.9.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.9.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 6.9.5.4.3 CPSW9G RGMII Timings
            1. 6.9.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.9.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 6.9.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.9.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 6.9.5.5  CSI-2
        6. 6.9.5.6  DDRSS
        7. 6.9.5.7  DSS
        8. 6.9.5.8  eCAP
          1. 6.9.5.8.1 Timing Requirements for eCAP
          2. 6.9.5.8.2 Switching Characteristics for eCAP
        9. 6.9.5.9  EPWM
          1. 6.9.5.9.1 Switching Characteristics for eHRPWM
          2. 6.9.5.9.2 Timing Requirements for eHRPWM
        10. 6.9.5.10 eQEP
          1. 6.9.5.10.1 Timing Requirements for eQEP
          2. 6.9.5.10.2 Switching Characteristics for eQEP
        11. 6.9.5.11 GPIO
          1. 6.9.5.11.1 GPIO Timing Requirements
          2. 6.9.5.11.2 GPIO Switching Characteristics
        12. 6.9.5.12 GPMC
          1. 6.9.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.9.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.9.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.9.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.9.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.9.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.9.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.9.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.9.5.12.4 GPMC0 IOSET
        13. 6.9.5.13 HyperBus
          1. 6.9.5.13.1 Timing Requirements for HyperBus
          2. 6.9.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 6.9.5.14 I2C
        15. 6.9.5.15 I3C
        16. 6.9.5.16 MCAN
        17. 6.9.5.17 MCASP
        18. 6.9.5.18 MCSPI
          1. 6.9.5.18.1 MCSPI — Master Mode
          2. 6.9.5.18.2 MCSPI — Slave Mode
        19. 6.9.5.19 MMCSD
          1. 6.9.5.19.1 MMC0 - eMMC Interface
            1. 6.9.5.19.1.1 Legacy SDR Mode
            2. 6.9.5.19.1.2 High Speed SDR Mode
            3. 6.9.5.19.1.3 High Speed DDR Mode
            4. 6.9.5.19.1.4 HS200 Mode
          2. 6.9.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 6.9.5.19.2.1 Default Speed Mode
            2. 6.9.5.19.2.2 High Speed Mode
            3. 6.9.5.19.2.3 UHS–I SDR12 Mode
            4. 6.9.5.19.2.4 UHS–I SDR25 Mode
            5. 6.9.5.19.2.5 UHS–I SDR50 Mode
            6. 6.9.5.19.2.6 UHS–I DDR50 Mode
            7. 6.9.5.19.2.7 UHS–I SDR104 Mode
        20. 6.9.5.20 CPTS
          1. 6.9.5.20.1 CPTS Timing Requirements
          2. 6.9.5.20.2 CPTS Switching Characteristics
        21. 6.9.5.21 OSPI
          1. 6.9.5.21.1 OSPI PHY Mode
            1. 6.9.5.21.1.1 OSPI With Data Training
              1. 6.9.5.21.1.1.1 OSPI Switching Characteristics – Data Training
            2. 6.9.5.21.1.2 OSPI Without Data Training
              1. 6.9.5.21.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.9.5.21.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.9.5.21.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.9.5.21.1.2.4 OSPI Switching Characteristics – DDR Mode
          2. 6.9.5.21.2 OSPI Tap Mode
            1. 6.9.5.21.2.1 OSPI Tap SDR Timing
            2. 6.9.5.21.2.2 OSPI Tap DDR Timing
        22. 6.9.5.22 PCIE
        23. 6.9.5.23 Timers
          1. 6.9.5.23.1 Timing Requirements for Timers
          2. 6.9.5.23.2 Switching Characteristics for Timers
        24. 6.9.5.24 UART
          1. 6.9.5.24.1 Timing Requirements for UART
          2. 6.9.5.24.2 UART Switching Characteristics
        25. 6.9.5.25 USB
      6. 6.9.6 Emulation and Debug
        1. 6.9.6.1 Trace
        2. 6.9.6.2 JTAG
          1. 6.9.6.2.1 JTAG Electrical Data and Timing
            1. 6.9.6.2.1.1 JTAG Timing Requirements
            2. 6.9.6.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A72
      2. 7.2.2 Arm Cortex-R5F
      3. 7.2.3 DSP C71x
      4. 7.2.4 DSP C66x
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 GPU
      2. 7.3.2 VPAC
      3. 7.3.3 DMPAC
      4. 7.3.4 D5520MP2
      5. 7.3.5 VXE384MP2
    4. 7.4 Other Subsystems
      1. 7.4.1 MSMC
      2. 7.4.2 NAVSS
        1. 7.4.2.1 NAVSS0
        2. 7.4.2.2 MCU_NAVSS
      3. 7.4.3 PDMA Controller
      4. 7.4.4 Power Supply
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  ATL
        3. 7.4.5.3  CSI
          1. 7.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 7.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 7.4.5.4  CPSW2G
        5. 7.4.5.5  CPSW9G
        6. 7.4.5.6  DCC
        7. 7.4.5.7  DDRSS
        8. 7.4.5.8  DSS
          1. 7.4.5.8.1 DSI
          2. 7.4.5.8.2 eDP
        9. 7.4.5.9  VPFE
        10. 7.4.5.10 eCAP
        11. 7.4.5.11 EPWM
        12. 7.4.5.12 ELM
        13. 7.4.5.13 ESM
        14. 7.4.5.14 eQEP
        15. 7.4.5.15 GPIO
        16. 7.4.5.16 GPMC
        17. 7.4.5.17 Hyperbus
        18. 7.4.5.18 I2C
        19. 7.4.5.19 I3C
        20. 7.4.5.20 MCAN
        21. 7.4.5.21 MCASP
        22. 7.4.5.22 MCRC Controller
        23. 7.4.5.23 MCSPI
        24. 7.4.5.24 MMC/SD
        25. 7.4.5.25 OSPI
        26. 7.4.5.26 PCIE
        27. 7.4.5.27 SerDes
        28. 7.4.5.28 WWDT
        29. 7.4.5.29 Timers
        30. 7.4.5.30 UART
        31. 7.4.5.31 USB
        32. 7.4.5.32 UFS
  9. 8 Applications and Implementation
    1. 8.1 Power Supply Mapping
    2. 8.2 Device Connection and Layout Fundamentals
      1. 8.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.2.1.1 Power Distribution Network Implementation Guidance
      2. 8.2.2 External Oscillator
      3. 8.2.3 JTAG and EMU
      4. 8.2.4 Reset
      5. 8.2.5 Unused Pins
      6. 8.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 8.3 Peripheral- and Interface-Specific Design Information
      1. 8.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 8.3.2.1 No Loopback and Internal Pad Loopback
        2. 8.3.2.2 External Board Loopback
        3. 8.3.2.3 DQS (only available in Octal Flash devices)
      3. 8.3.3 SERDES REFCLK Design Guidelines
      4. 8.3.4 USB VBUS Design Guidelines
      5. 8.3.5 System Power Supply Monitor Design Guidelines
      6. 8.3.6 High Speed Differential Signal Routing Guidance
      7. 8.3.7 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • ALF|827
サーマルパッド・メカニカル・データ
発注情報

5.4 Pin Multiplexing

Note:

Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions.

Table 5-125, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see Pad Configuration Registers section in Device Configuration chapter in the device TRM. Refer to the respective peripheral chapter in the device TRM for information associated with peripheral signal multiplexing.

Note:

When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.

Note:

Table 5-125, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes) chapter in the device TRM.

Note:

Table 5-125, Pin Multiplexing does not include DPHY_TX signal functions. For more information, refer to the Shared D-PHY Transmitter (DPHY_TX) chapter in the device TRM.

For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM.

Table 5-125 Pin Multiplexing
ADDRESSREGISTER NAMEBALL NUMBERMUXMODE[14:0] SETTINGS
01234567891011121314Bootstrap
0x00011C294PADCONFIG165 AD1MLB0_MLBSPGPIO1_30
0x00011C29CPADCONFIG167 AC3MLB0_MLBDPGPIO1_32
0x00011C290PADCONFIG164 U6USB0_DRVVBUSUSB1_DRVVBUSGPIO1_29
0x00011C298PADCONFIG166 AC1MLB0_MLBSNGPIO1_31
0x00011C2A0PADCONFIG168 AD3MLB0_MLBDNGPIO1_33
0x00011C2A4PADCONFIG169 AD2MLB0_MLBCPGPIO1_34
0x00011C2A8PADCONFIG170 AE2MLB0_MLBCNGPIO1_35
0x00011C000PADCONFIG0 AC18EXTINTnGPIO0_0
0x00011C004PADCONFIG1 AC23PRG1_PRU0_GPO0PRG1_PRU0_GPI0PRG1_RGMII1_RD0PRG1_PWM3_A0RGMII1_RD0RMII1_RXD0GPIO0_1GPMC0_BE1nRGMII7_RD0MCASP6_ACLKXUART0_RXD
0x00011C008PADCONFIG2 AG22PRG1_PRU0_GPO1PRG1_PRU0_GPI1PRG1_RGMII1_RD1PRG1_PWM3_B0RGMII1_RD1RMII1_RXD1GPIO0_2GPMC0_WAIT0RGMII7_RD1MCASP6_AFSXUART0_TXD
0x00011C00CPADCONFIG3 AF22PRG1_PRU0_GPO2PRG1_PRU0_GPI2PRG1_RGMII1_RD2PRG1_PWM2_A0RGMII1_RD2RMII1_CRS_DVGPIO0_3GPMC0_WAIT1RGMII7_RD2MCASP6_AXR0UART1_RXD
0x00011C010PADCONFIG4 AJ23PRG1_PRU0_GPO3PRG1_PRU0_GPI3PRG1_RGMII1_RD3PRG1_PWM3_A2RGMII1_RD3RMII1_RX_ERGPIO0_4GPMC0_DIRRGMII7_RD3MCASP6_AXR1UART1_TXD
0x00011C014PADCONFIG5 AH23PRG1_PRU0_GPO4PRG1_PRU0_GPI4PRG1_RGMII1_RX_CTLPRG1_PWM2_B0RGMII1_RX_CTLRMII1_TXD0GPIO0_5GPMC0_CSn2RGMII7_RX_CTLMCASP6_AXR2MCASP6_ACLKRUART2_RXD
0x00011C018PADCONFIG6 AD20PRG1_PRU0_GPO5PRG1_PRU0_GPI5PRG1_PWM3_B2RMII1_TX_ENGPIO0_6GPMC0_WEnMCASP3_AXR0BOOTMODE0
0x00011C01CPADCONFIG7 AD22PRG1_PRU0_GPO6PRG1_PRU0_GPI6PRG1_RGMII1_RXCPRG1_PWM3_A1RGMII1_RXCRMII1_TXD1AUDIO_EXT_REFCLK0GPIO0_7GPMC0_CSn3RGMII7_RXCMCASP6_AXR3MCASP6_AFSRUART2_TXD
0x00011C020PADCONFIG8 AE20PRG1_PRU0_GPO7PRG1_PRU0_GPI7PRG1_IEP0_EDC_LATCH_IN1PRG1_PWM3_B1AUDIO_EXT_REFCLK1MCAN4_TXGPIO0_8MCASP3_AXR1
0x00011C024PADCONFIG9 AJ20PRG1_PRU0_GPO8PRG1_PRU0_GPI8PRG1_PWM2_A1RMII5_RXD0MCAN4_RXGPIO0_9GPMC0_OEn_REnVOUT0_DATA22MCASP3_AXR2
0x00011C028PADCONFIG10 AG20PRG1_PRU0_GPO9PRG1_PRU0_GPI9PRG1_UART0_CTSnPRG1_PWM3_TZ_INSPI6_CS1RMII5_RXD1GPIO0_10GPMC0_ADVn_ALEPRG1_IEP0_EDIO_DATA_IN_OUT28VOUT0_DATA23MCASP3_ACLKX
0x00011C02CPADCONFIG11 AD21PRG1_PRU0_GPO10PRG1_PRU0_GPI10PRG1_UART0_RTSnPRG1_PWM2_B1SPI6_CS2RMII5_CRS_DVGPIO0_11GPMC0_BE0n_CLEPRG1_IEP0_EDIO_DATA_IN_OUT29OBSCLK2MCASP3_AFSX
0x00011C030PADCONFIG12 AF24PRG1_PRU0_GPO11PRG1_PRU0_GPI11PRG1_RGMII1_TD0PRG1_PWM3_TZ_OUTRGMII1_TD0MCAN4_TXGPIO0_12RGMII7_TD0VOUT0_DATA16VPFE0_DATA0MCASP7_ACLKX
0x00011C034PADCONFIG13 AJ24PRG1_PRU0_GPO12PRG1_PRU0_GPI12PRG1_RGMII1_TD1PRG1_PWM0_A0RGMII1_TD1MCAN4_RXGPIO0_13RGMII7_TD1VOUT0_DATA17VPFE0_DATA1MCASP7_AFSX
0x00011C038PADCONFIG14 AG24PRG1_PRU0_GPO13PRG1_PRU0_GPI13PRG1_RGMII1_TD2PRG1_PWM0_B0RGMII1_TD2MCAN5_TXGPIO0_14RGMII7_TD2VOUT0_DATA18VPFE0_DATA2MCASP7_AXR0
0x00011C03CPADCONFIG15 AD24PRG1_PRU0_GPO14PRG1_PRU0_GPI14PRG1_RGMII1_TD3PRG1_PWM0_A1RGMII1_TD3MCAN5_RXGPIO0_15RGMII7_TD3VOUT0_DATA19VPFE0_DATA3MCASP7_AXR1
0x00011C040PADCONFIG16 AC24PRG1_PRU0_GPO15PRG1_PRU0_GPI15PRG1_RGMII1_TX_CTLPRG1_PWM0_B1RGMII1_TX_CTLMCAN6_TXGPIO0_16RGMII7_TX_CTLVOUT0_DATA20VPFE0_DATA4MCASP7_AXR2MCASP7_ACLKR
0x00011C044PADCONFIG17 AE24PRG1_PRU0_GPO16PRG1_PRU0_GPI16PRG1_RGMII1_TXCPRG1_PWM0_A2RGMII1_TXCMCAN6_RXGPIO0_17RGMII7_TXCVOUT0_DATA21VPFE0_DATA5MCASP7_AXR3MCASP7_AFSR
0x00011C04CPADCONFIG19 AJ21PRG1_PRU0_GPO17PRG1_PRU0_GPI17PRG1_IEP0_EDC_SYNC_OUT1PRG1_PWM0_B2RMII5_TXD1MCAN5_TXGPIO0_18VPFE0_DATA6MCASP3_AXR3
0x00011C050PADCONFIG20 AE21PRG1_PRU0_GPO18PRG1_PRU0_GPI18PRG1_IEP0_EDC_LATCH_IN0PRG1_PWM0_TZ_INRMII5_RX_ERMCAN5_RXGPIO0_19VPFE0_DATA7MCASP4_ACLKX
0x00011C054PADCONFIG21 AH21PRG1_PRU0_GPO19PRG1_PRU0_GPI19PRG1_IEP0_EDC_SYNC_OUT0PRG1_PWM0_TZ_OUTRMII5_TXD0MCAN6_TXGPIO0_20VOUT0_EXTPCLKINVPFE0_PCLKMCASP4_AFSX
0x00011C058PADCONFIG22 AE22PRG1_PRU1_GPO0PRG1_PRU1_GPI0PRG1_RGMII2_RD0RGMII2_RD0RMII2_RXD0GPIO0_21RGMII8_RD0VOUT0_DATA0VPFE0_HDMCASP8_ACLKX
0x00011C05CPADCONFIG23 AG23PRG1_PRU1_GPO1PRG1_PRU1_GPI1PRG1_RGMII2_RD1RGMII2_RD1RMII2_RXD1GPIO0_22RGMII8_RD1VOUT0_DATA1VPFE0_FIELDMCASP8_AFSX
0x00011C060PADCONFIG24 AF23PRG1_PRU1_GPO2PRG1_PRU1_GPI2PRG1_RGMII2_RD2PRG1_PWM2_A2RGMII2_RD2RMII2_CRS_DVGPIO0_23RGMII8_RD2VOUT0_DATA2VPFE0_VDMCASP8_AXR0MCASP3_ACLKR
0x00011C064PADCONFIG25 AD23PRG1_PRU1_GPO3PRG1_PRU1_GPI3PRG1_RGMII2_RD3RGMII2_RD3RMII2_RX_ERGPIO0_24RGMII8_RD3EQEP1_AVOUT0_DATA3VPFE0_WENMCASP8_AXR1MCASP3_AFSRTIMER_IO2
0x00011C068PADCONFIG26 AH24PRG1_PRU1_GPO4PRG1_PRU1_GPI4PRG1_RGMII2_RX_CTLPRG1_PWM2_B2RGMII2_RX_CTLRMII2_TXD0GPIO0_25RGMII8_RX_CTLEQEP1_BVOUT0_DATA4VPFE0_DATA13MCASP8_AXR2MCASP8_ACLKRTIMER_IO3
0x00011C06CPADCONFIG27 AG21PRG1_PRU1_GPO5PRG1_PRU1_GPI5RMII5_TX_ENMCAN6_RXGPIO0_26GPMC0_WPnEQEP1_SVOUT0_DATA5MCASP4_AXR0TIMER_IO4
0x00011C070PADCONFIG28 AE23PRG1_PRU1_GPO6PRG1_PRU1_GPI6PRG1_RGMII2_RXCRGMII2_RXCRMII2_TXD1GPIO0_27RGMII8_RXCVOUT0_DATA6VPFE0_DATA14MCASP8_AXR3MCASP8_AFSRTIMER_IO5
0x00011C074PADCONFIG29 AC21PRG1_PRU1_GPO7PRG1_PRU1_GPI7PRG1_IEP1_EDC_LATCH_IN1SPI6_CS0RMII6_RX_ERMCAN7_TXGPIO0_28VOUT0_DATA7VPFE0_DATA15MCASP4_AXR1UART3_TXD
0x00011C078PADCONFIG30 Y23PRG1_PRU1_GPO8PRG1_PRU1_GPI8PRG1_PWM2_TZ_OUTRMII6_RXD0MCAN7_RXGPIO0_29GPMC0_CSn1VOUT0_DATA8MCASP4_AXR2UART3_RXD
0x00011C07CPADCONFIG31 AF21PRG1_PRU1_GPO9PRG1_PRU1_GPI9PRG1_UART0_RXDSPI6_CS3RMII6_RXD1MCAN8_TXGPIO0_30GPMC0_CSn0PRG1_IEP0_EDIO_DATA_IN_OUT30VOUT0_DATA9MCASP4_AXR3
0x00011C080PADCONFIG32 AB23PRG1_PRU1_GPO10PRG1_PRU1_GPI10PRG1_UART0_TXDPRG1_PWM2_TZ_INRMII6_CRS_DVMCAN8_RXGPIO0_31GPMC0_CLKOUTPRG1_IEP0_EDIO_DATA_IN_OUT31VOUT0_DATA10GPMC0_FCLK_MUXMCASP5_ACLKX
0x00011C084PADCONFIG33 AJ25PRG1_PRU1_GPO11PRG1_PRU1_GPI11PRG1_RGMII2_TD0RGMII2_TD0RMII2_TX_ENGPIO0_32RGMII8_TD0EQEP1_IVOUT0_DATA11MCASP9_ACLKX
0x00011C088PADCONFIG34 AH25PRG1_PRU1_GPO12PRG1_PRU1_GPI12PRG1_RGMII2_TD1PRG1_PWM1_A0RGMII2_TD1MCAN7_TXGPIO0_33RGMII8_TD1VOUT0_DATA12MCASP9_AFSX
0x00011C08CPADCONFIG35 AG25PRG1_PRU1_GPO13PRG1_PRU1_GPI13PRG1_RGMII2_TD2PRG1_PWM1_B0RGMII2_TD2MCAN7_RXGPIO0_34RGMII8_TD2VOUT0_DATA13VPFE0_DATA8MCASP9_AXR0MCASP4_ACLKR
0x00011C090PADCONFIG36 AH26PRG1_PRU1_GPO14PRG1_PRU1_GPI14PRG1_RGMII2_TD3PRG1_PWM1_A1RGMII2_TD3MCAN8_TXGPIO0_35RGMII8_TD3VOUT0_DATA14MCASP9_AXR1MCASP4_AFSR
0x00011C094PADCONFIG37 AJ27PRG1_PRU1_GPO15PRG1_PRU1_GPI15PRG1_RGMII2_TX_CTLPRG1_PWM1_B1RGMII2_TX_CTLMCAN8_RXGPIO0_36RGMII8_TX_CTLVOUT0_DATA15VPFE0_DATA9MCASP9_AXR2MCASP9_ACLKR
0x00011C098PADCONFIG38 AJ26PRG1_PRU1_GPO16PRG1_PRU1_GPI16PRG1_RGMII2_TXCPRG1_PWM1_A2RGMII2_TXCGPIO0_37RGMII8_TXCVOUT0_VP2_HSYNCVOUT0_HSYNCMCASP9_AXR3MCASP9_AFSRVOUT0_VP0_HSYNC
0x00011C09CPADCONFIG39 AC22PRG1_PRU1_GPO17PRG1_PRU1_GPI17PRG1_IEP1_EDC_SYNC_OUT1PRG1_PWM1_B2SPI6_CLKRMII6_TX_ENPRG1_ECAP0_SYNC_OUTGPIO0_38VOUT0_VP2_DEVOUT0_DEVPFE0_DATA10MCASP5_AFSXVOUT0_VP0_DEBOOTMODE1
0x00011C0A0PADCONFIG40 AJ22PRG1_PRU1_GPO18PRG1_PRU1_GPI18PRG1_IEP1_EDC_LATCH_IN0PRG1_PWM1_TZ_INSPI6_D0RMII6_TXD0PRG1_ECAP0_SYNC_INGPIO0_39VOUT0_VP2_VSYNCVOUT0_VSYNCMCASP5_AXR0VOUT0_VP0_VSYNC
0x00011C0A4PADCONFIG41 AH22PRG1_PRU1_GPO19PRG1_PRU1_GPI19PRG1_IEP1_EDC_SYNC_OUT0PRG1_PWM1_TZ_OUTSPI6_D1RMII6_TXD1PRG1_ECAP0_IN_APWM_OUTGPIO0_40VOUT0_PCLKMCASP5_AXR1
0x00011C0A8PADCONFIG42 AD19PRG1_MDIO0_MDIOSPI1_CS2I2C4_SCLGPIO0_41DSS_FSYNC1VPFE0_DATA11MCASP5_AXR2MCASP5_ACLKRUART3_CTSn
0x00011C0ACPADCONFIG43 AD18PRG1_MDIO0_MDCSPI1_CS3I2C4_SDARMII_REF_CLKGPIO0_42VPFE0_DATA12MCASP5_AXR3MCASP5_AFSRUART3_RTSn
0x00011C0B0PADCONFIG44 AF28PRG0_PRU0_GPO0PRG0_PRU0_GPI0PRG0_RGMII1_RD0PRG0_PWM3_A0RGMII3_RD0RMII3_RXD1GPIO0_43MCASP0_AXR0
0x00011C0B4PADCONFIG45 AE28PRG0_PRU0_GPO1PRG0_PRU0_GPI1PRG0_RGMII1_RD1PRG0_PWM3_B0RGMII3_RD1RMII3_RXD0GPIO0_44MCASP0_AXR1
0x00011C0B8PADCONFIG46 AE27PRG0_PRU0_GPO2PRG0_PRU0_GPI2PRG0_RGMII1_RD2PRG0_PWM2_A0RGMII3_RD2RMII3_CRS_DVGPIO0_45UART3_RXDMCASP0_ACLKR
0x00011C0BCPADCONFIG47 AD26PRG0_PRU0_GPO3PRG0_PRU0_GPI3PRG0_RGMII1_RD3PRG0_PWM3_A2RGMII3_RD3RMII3_RX_ERGPIO0_46UART3_TXDMCASP0_AFSR
0x00011C0C0PADCONFIG48 AD25PRG0_PRU0_GPO4PRG0_PRU0_GPI4PRG0_RGMII1_RX_CTLPRG0_PWM2_B0RGMII3_RX_CTLRMII3_TXD1GPIO0_47MCASP0_AXR2
0x00011C0C4PADCONFIG49 AC29PRG0_PRU0_GPO5PRG0_PRU0_GPI5PRG0_PWM3_B2RMII3_TXD0GPIO0_48GPMC0_AD0MCASP0_AXR3BOOTMODE2
0x00011C0C8PADCONFIG50 AE26PRG0_PRU0_GPO6PRG0_PRU0_GPI6PRG0_RGMII1_RXCPRG0_PWM3_A1RGMII3_RXCRMII3_TX_ENGPIO0_49MCASP0_AXR4
0x00011C0CCPADCONFIG51 AC28PRG0_PRU0_GPO7PRG0_PRU0_GPI7PRG0_IEP0_EDC_LATCH_IN1PRG0_PWM3_B1PRG0_ECAP0_SYNC_INMCAN9_TXGPIO0_50GPMC0_AD1MCASP0_AXR5
0x00011C0D0PADCONFIG52 AC27PRG0_PRU0_GPO8PRG0_PRU0_GPI8PRG0_PWM2_A1MCAN9_RXGPIO0_51GPMC0_AD2MCASP0_AXR6UART6_RXD
0x00011C0D4PADCONFIG53 AB26PRG0_PRU0_GPO9PRG0_PRU0_GPI9PRG0_UART0_CTSnPRG0_PWM3_TZ_INSPI3_CS1PRG0_IEP0_EDIO_DATA_IN_OUT28MCAN10_TXGPIO0_52GPMC0_AD3MCASP0_ACLKXUART6_TXD
0x00011C0D8PADCONFIG54 AB25PRG0_PRU0_GPO10PRG0_PRU0_GPI10PRG0_UART0_RTSnPRG0_PWM2_B1SPI3_CS2PRG0_IEP0_EDIO_DATA_IN_OUT29MCAN10_RXGPIO0_53GPMC0_AD4MCASP0_AFSX
0x00011C0DCPADCONFIG55 AJ28PRG0_PRU0_GPO11PRG0_PRU0_GPI11PRG0_RGMII1_TD0PRG0_PWM3_TZ_OUTRGMII3_TD0GPIO0_54CLKOUTMCASP0_AXR7
0x00011C0E0PADCONFIG56 AH27PRG0_PRU0_GPO12PRG0_PRU0_GPI12PRG0_RGMII1_TD1PRG0_PWM0_A0RGMII3_TD1GPIO0_55DSS_FSYNC0MCASP0_AXR8
0x00011C0E4PADCONFIG57 AH29PRG0_PRU0_GPO13PRG0_PRU0_GPI13PRG0_RGMII1_TD2PRG0_PWM0_B0RGMII3_TD2GPIO0_56DSS_FSYNC2MCASP0_AXR9
0x00011C0E8PADCONFIG58 AG28PRG0_PRU0_GPO14PRG0_PRU0_GPI14PRG0_RGMII1_TD3PRG0_PWM0_A1RGMII3_TD3GPIO0_57UART4_RXDMCASP0_AXR10
0x00011C0ECPADCONFIG59 AG27PRG0_PRU0_GPO15PRG0_PRU0_GPI15PRG0_RGMII1_TX_CTLPRG0_PWM0_B1RGMII3_TX_CTLGPIO0_58UART4_TXDDSS_FSYNC3MCASP0_AXR11
0x00011C0F0PADCONFIG60 AH28PRG0_PRU0_GPO16PRG0_PRU0_GPI16PRG0_RGMII1_TXCPRG0_PWM0_A2RGMII3_TXCGPIO0_59DSS_FSYNC1MCASP0_AXR12
0x00011C0F4PADCONFIG61 AB24PRG0_PRU0_GPO17PRG0_PRU0_GPI17PRG0_IEP0_EDC_SYNC_OUT1PRG0_PWM0_B2PRG0_ECAP0_SYNC_OUTGPIO0_60GPMC0_AD5OBSCLK1MCASP0_AXR13BOOTMODE7
0x00011C0F8PADCONFIG62 AB29PRG0_PRU0_GPO18PRG0_PRU0_GPI18PRG0_IEP0_EDC_LATCH_IN0PRG0_PWM0_TZ_INPRG0_ECAP0_IN_APWM_OUTGPIO0_61GPMC0_AD6MCASP0_AXR14
0x00011C0FCPADCONFIG63 AB28PRG0_PRU0_GPO19PRG0_PRU0_GPI19PRG0_IEP0_EDC_SYNC_OUT0PRG0_PWM0_TZ_OUTGPIO0_62GPMC0_AD7MCASP0_AXR15
0x00011C100PADCONFIG64 AE29PRG0_PRU1_GPO0PRG0_PRU1_GPI0PRG0_RGMII2_RD0RGMII4_RD0RMII4_RXD0GPIO0_63UART4_CTSnMCASP1_AXR0UART5_RXD
0x00011C104PADCONFIG65 AD28PRG0_PRU1_GPO1PRG0_PRU1_GPI1PRG0_RGMII2_RD1RGMII4_RD1RMII4_RXD1GPIO0_64UART4_RTSnMCASP1_AXR1UART5_TXD
0x00011C108PADCONFIG66 AD27PRG0_PRU1_GPO2PRG0_PRU1_GPI2PRG0_RGMII2_RD2PRG0_PWM2_A2RGMII4_RD2RMII4_CRS_DVGPIO0_65GPMC0_A23MCASP1_ACLKRMCASP1_AXR10
0x00011C10CPADCONFIG67 AC25PRG0_PRU1_GPO3PRG0_PRU1_GPI3PRG0_RGMII2_RD3RGMII4_RD3RMII4_RX_ERGPIO0_66MCASP1_AFSRMCASP1_AXR11
0x00011C110PADCONFIG68 AD29PRG0_PRU1_GPO4PRG0_PRU1_GPI4PRG0_RGMII2_RX_CTLPRG0_PWM2_B2RGMII4_RX_CTLRMII4_TXD1GPIO0_67GPMC0_A24MCASP1_AXR2
0x00011C114PADCONFIG69 AB27PRG0_PRU1_GPO5PRG0_PRU1_GPI5GPIO0_68GPMC0_AD8MCASP1_ACLKXBOOTMODE6
0x00011C118PADCONFIG70 AC26PRG0_PRU1_GPO6PRG0_PRU1_GPI6PRG0_RGMII2_RXCRGMII4_RXCRMII4_TXD0GPIO0_69GPMC0_A25MCASP1_AXR3
0x00011C11CPADCONFIG71 AA24PRG0_PRU1_GPO7PRG0_PRU1_GPI7PRG0_IEP1_EDC_LATCH_IN1SPI3_CS0MCAN11_TXGPIO0_70GPMC0_AD9MCASP1_AXR4UART2_TXD
0x00011C120PADCONFIG72 AA28PRG0_PRU1_GPO8PRG0_PRU1_GPI8PRG0_PWM2_TZ_OUTMCAN11_RXGPIO0_71GPMC0_AD10MCASP1_AFSX
0x00011C124PADCONFIG73 Y24PRG0_PRU1_GPO9PRG0_PRU1_GPI9PRG0_UART0_RXDSPI3_CS3PRG0_IEP0_EDIO_DATA_IN_OUT30GPIO0_72GPMC0_AD11DSS_FSYNC3MCASP1_AXR5UART8_RXD
0x00011C128PADCONFIG74 AA25PRG0_PRU1_GPO10PRG0_PRU1_GPI10PRG0_UART0_TXDPRG0_PWM2_TZ_INPRG0_IEP0_EDIO_DATA_IN_OUT31GPIO0_73GPMC0_AD12CLKOUTMCASP1_AXR6UART8_TXD
0x00011C12CPADCONFIG75 AG26PRG0_PRU1_GPO11PRG0_PRU1_GPI11PRG0_RGMII2_TD0RGMII4_TD0RMII4_TX_ENGPIO0_74GPMC0_A26MCASP1_AXR7
0x00011C130PADCONFIG76 AF27PRG0_PRU1_GPO12PRG0_PRU1_GPI12PRG0_RGMII2_TD1PRG0_PWM1_A0RGMII4_TD1GPIO0_75MCASP1_AXR8UART8_CTSn
0x00011C134PADCONFIG77 AF26PRG0_PRU1_GPO13PRG0_PRU1_GPI13PRG0_RGMII2_TD2PRG0_PWM1_B0RGMII4_TD2GPIO0_76MCASP1_AXR9UART8_RTSn
0x00011C138PADCONFIG78 AE25PRG0_PRU1_GPO14PRG0_PRU1_GPI14PRG0_RGMII2_TD3PRG0_PWM1_A1RGMII4_TD3GPIO0_77MCASP2_AXR0UART2_CTSn
0x00011C13CPADCONFIG79 AF29PRG0_PRU1_GPO15PRG0_PRU1_GPI15PRG0_RGMII2_TX_CTLPRG0_PWM1_B1RGMII4_TX_CTLGPIO0_78MCASP2_AXR1UART2_RTSn
0x00011C140PADCONFIG80 AG29PRG0_PRU1_GPO16PRG0_PRU1_GPI16PRG0_RGMII2_TXCPRG0_PWM1_A2RGMII4_TXCGPIO0_79MCASP2_AXR2
0x00011C144PADCONFIG81 Y25PRG0_PRU1_GPO17PRG0_PRU1_GPI17PRG0_IEP1_EDC_SYNC_OUT1PRG0_PWM1_B2SPI3_CLKGPIO0_80GPMC0_AD13MCASP2_AXR3BOOTMODE3
0x00011C148PADCONFIG82 AA26PRG0_PRU1_GPO18PRG0_PRU1_GPI18PRG0_IEP1_EDC_LATCH_IN0PRG0_PWM1_TZ_INSPI3_D0MCAN12_TXGPIO0_81GPMC0_AD14MCASP2_AFSXUART2_RXD
0x00011C14CPADCONFIG83 AA29PRG0_PRU1_GPO19PRG0_PRU1_GPI19PRG0_IEP1_EDC_SYNC_OUT0PRG0_PWM1_TZ_OUTSPI3_D1MCAN12_RXGPIO0_82GPMC0_AD15MCASP2_ACLKX
0x00011C150PADCONFIG84 Y26PRG0_MDIO0_MDIOI2C5_SCLMCAN13_TXGPIO0_83GPMC0_A27DSS_FSYNC0MCASP2_AFSRMCASP2_AXR4
0x00011C154PADCONFIG85 AA27PRG0_MDIO0_MDCI2C5_SDAMCAN13_RXGPIO0_84GPMC0_A0DSS_FSYNC2MCASP2_ACLKRMCASP2_AXR5
0x00011C158PADCONFIG86 U23RGMII5_TX_CTLRMII7_CRS_DVI2C2_SCLVOUT1_DATA0TRC_CLKEHRPWM0_SYNCIGPIO0_85GPMC0_A1MCASP10_ACLKX
0x00011C15CPADCONFIG87 U26RGMII5_RX_CTLRMII7_RX_ERI2C2_SDAVOUT1_DATA1TRC_CTLEHRPWM0_SYNCOGPIO0_86GPMC0_A2MCASP10_AFSX
0x00011C160PADCONFIG88 V28RGMII5_TD3UART3_RXDSYNC2_OUTVOUT1_DATA2TRC_DATA0EHRPWM_TZn_IN0GPIO0_87GPMC0_A3MCASP10_AXR0
0x00011C164PADCONFIG89 V29RGMII5_TD2UART3_TXDSYNC3_OUTVOUT1_DATA3TRC_DATA1EHRPWM0_AGPIO0_88GPMC0_A4MCASP10_AXR1
0x00011C168PADCONFIG90 V27RGMII5_TD1RMII7_TXD1I2C3_SCLVOUT1_DATA4TRC_DATA2EHRPWM0_BGPIO0_89GPMC0_A5MCASP11_ACLKX
0x00011C16CPADCONFIG91 U28RGMII5_TD0RMII7_TXD0I2C3_SDAVOUT1_DATA5TRC_DATA3EHRPWM1_AGPIO0_90GPMC0_A6MCASP11_AFSX
0x00011C170PADCONFIG92 U29RGMII5_TXCRMII7_TX_ENI2C6_SCLVOUT1_DATA6TRC_DATA4EHRPWM1_BGPIO0_91GPMC0_A7MCASP10_AXR2
0x00011C174PADCONFIG93 U25RGMII5_RXCI2C6_SDAVOUT1_DATA7TRC_DATA5EHRPWM_TZn_IN1GPIO0_92GPMC0_A8MCASP10_AXR3EHRPWM_SOCA
0x00011C178PADCONFIG94 U27RGMII5_RD3UART3_CTSnUART6_RXDVOUT1_DATA8TRC_DATA6EHRPWM2_AGPIO0_93GPMC0_A9MCASP11_AXR0
0x00011C17CPADCONFIG95 U24RGMII5_RD2UART3_RTSnUART6_TXDVOUT1_DATA9TRC_DATA7EHRPWM2_BGPIO0_94GPMC0_A10MCASP11_AXR1
0x00011C180PADCONFIG96 R23RGMII5_RD1RMII7_RXD1UART6_CTSnVOUT1_DATA10TRC_DATA8EHRPWM_TZn_IN2GPIO0_95GPMC0_A11MCASP11_AXR2EHRPWM_SOCB
0x00011C184PADCONFIG97 T23RGMII5_RD0RMII7_RXD0UART6_RTSnVOUT1_DATA11TRC_DATA9GPIO0_96GPMC0_A12MCASP11_AXR3
0x00011C188PADCONFIG98 Y28RGMII6_TX_CTLRMII8_CRS_DVVOUT1_DATA12TRC_DATA10GPIO0_97GPMC0_A13MCASP10_ACLKR
0x00011C18CPADCONFIG99 V23RGMII6_RX_CTLRMII8_RX_ERVOUT1_DATA13TRC_DATA11EHRPWM3_AGPIO0_98GPMC0_A14MCASP10_AFSR
0x00011C190PADCONFIG100 W23RGMII6_TD3UART4_RXDSPI5_CS3VOUT1_DATA14TRC_DATA12EHRPWM3_BGPIO0_99GPMC0_A15MCASP11_ACLKR
0x00011C194PADCONFIG101 W28RGMII6_TD2UART4_TXDSPI5_CS2VOUT1_DATA15TRC_DATA13EHRPWM3_SYNCIGPIO0_100GPMC0_A16MCASP11_AFSR
0x00011C198PADCONFIG102 V25RGMII6_TD1RMII8_TXD1SPI5_D0VOUT1_VSYNCTRC_DATA14EHRPWM3_SYNCOGPIO0_101GPMC0_A17VOUT1_VP0_VSYNCMCASP10_AXR4
0x00011C19CPADCONFIG103 W27RGMII6_TD0RMII8_TXD0SPI5_CS0VOUT1_HSYNCTRC_DATA15EHRPWM_TZn_IN3GPIO0_102GPMC0_A18VOUT1_VP0_HSYNCMCASP10_AXR5
0x00011C1A0PADCONFIG104 W29RGMII6_TXCRMII8_TX_ENSPI5_CLKVOUT1_PCLKTRC_DATA16EHRPWM4_AGPIO0_103GPMC0_A19MCASP10_AXR6
0x00011C1A4PADCONFIG105 W26RGMII6_RXCAUDIO_EXT_REFCLK2VOUT1_DETRC_DATA17EHRPWM4_BGPIO0_104GPMC0_A20VOUT1_VP0_DEMCASP10_AXR7
0x00011C1A8PADCONFIG106 Y29RGMII6_RD3UART4_CTSnUART5_RXDCLKOUTTRC_DATA18EHRPWM_TZn_IN4GPIO0_105GPMC0_A21MCASP11_AXR4
0x00011C1ACPADCONFIG107 Y27RGMII6_RD2UART4_RTSnUART5_TXDTRC_DATA19EHRPWM5_AGPIO0_106GPMC0_A22MCASP11_AXR5
0x00011C1B0PADCONFIG108 W24RGMII6_RD1RMII8_RXD1SPI5_D1VOUT1_EXTPCLKINTRC_DATA20EHRPWM5_BGPIO0_107GPMC0_BE1nMCASP11_AXR6
0x00011C1B4PADCONFIG109 W25RGMII6_RD0RMII8_RXD0SPI5_CS1AUDIO_EXT_REFCLK3TRC_DATA21EHRPWM_TZn_IN5GPIO0_108GPMC0_DIRMCASP11_AXR7
0x00011C1B8PADCONFIG110 V26MDIO0_MDIOTRC_DATA22GPIO0_109GPMC0_WAIT3
0x00011C1BCPADCONFIG111 V24MDIO0_MDCTRC_DATA23GPIO0_110GPMC0_WAIT2
0x00011C1C0PADCONFIG112 AA2SPI0_CS0UART0_RTSnGPIO0_111
0x00011C1C4PADCONFIG113 Y4SPI0_CS1CPTS0_TS_COMPI2C3_SCLDP0_HPDPRG1_IEP0_EDIO_OUTVALIDGPIO0_112
0x00011C1C8PADCONFIG114 AA1SPI0_CLKUART1_CTSnI2C2_SCLGPIO0_113
0x00011C1CCPADCONFIG115 AB5SPI0_D0UART1_RTSnI2C2_SDAGPIO0_114
0x00011C1D0PADCONFIG116 AA3SPI0_D1I2C6_SCLGPIO0_115
0x00011C1D4PADCONFIG117 Y3SPI1_CS0UART0_CTSnUART5_RXDPRG0_IEP0_EDIO_OUTVALIDGPIO0_116PRG0_IEP0_EDC_LATCH_IN0
0x00011C1D8PADCONFIG118 W4SPI1_CS1CPTS0_TS_SYNCI2C3_SDAUART5_TXDGPIO0_117
0x00011C1DCPADCONFIG119 Y1SPI1_CLKUART5_CTSnI2C4_SDAUART2_RXDGPIO0_118PRG0_IEP0_EDC_SYNC_OUT0
0x00011C1E0PADCONFIG120 Y5SPI1_D0UART5_RTSnI2C4_SCLUART2_TXDGPIO0_119PRG0_IEP1_EDC_LATCH_IN0
0x00011C1E4PADCONFIG121 Y2SPI1_D1I2C6_SDAGPIO0_120PRG0_IEP1_EDC_SYNC_OUT0
0x00011C1E8PADCONFIG122 AB2UART0_RXDSPI2_CS1GPIO0_121
0x00011C1ECPADCONFIG123 AB3UART0_TXDSPI2_CS2SPI7_CS1GPIO0_122
0x00011C1F0PADCONFIG124 AC2UART0_CTSnTIMER_IO6SPI0_CS2MCAN2_RXSPI2_CS0EQEP0_AGPIO0_123
0x00011C1F4PADCONFIG125 AB1UART0_RTSnTIMER_IO7SPI0_CS3MCAN2_TXSPI2_CLKEQEP0_BGPIO0_124
0x00011C1F8PADCONFIG126 AA4UART1_RXDSPI7_CS2GPIO0_125
0x00011C1FCPADCONFIG127 AB4UART1_TXDI3C0_SDAPULLENSPI7_CS3GPIO0_126
0x00011C200PADCONFIG128 AC4UART1_CTSnMCAN3_RXSPI2_D0EQEP0_SGPIO0_127
0x00011C204PADCONFIG129 AD5UART1_RTSnMCAN3_TXSPI2_D1EQEP0_IGPIO1_0
0x00011C208PADCONFIG130 W5MCAN0_RXI2C2_SCLGPIO1_1
0x00011C20CPADCONFIG131 W6MCAN0_TXI2C2_SDAGPIO1_2
0x00011C210PADCONFIG132 W3MCAN1_RXUART6_CTSnUART9_RXDUSB0_DRVVBUSUSB1_DRVVBUSGPIO1_3
0x00011C214PADCONFIG133 V4MCAN1_TXUART6_RTSnUART9_TXDUSB0_DRVVBUSUSB1_DRVVBUSGPIO1_4
0x00011C218PADCONFIG134 W2I3C0_SCLMMC2_SDCDUART9_CTSnMCAN2_RXI2C6_SCLDP0_HPDPCIE0_CLKREQnGPIO1_5UART6_RXD
0x00011C21CPADCONFIG135 W1I3C0_SDAMMC2_SDWPUART9_RTSnMCAN2_TXI2C6_SDAPCIE1_CLKREQnGPIO1_6UART6_TXD
0x00011C220PADCONFIG136 AC5I2C0_SCLGPIO1_7
0x00011C224PADCONFIG137 AA5I2C0_SDAGPIO1_8
0x00011C228PADCONFIG138 Y6I2C1_SCLCPTS0_HW1TSPUSHGPIO1_9
0x00011C22CPADCONFIG139 AA6I2C1_SDACPTS0_HW2TSPUSHGPIO1_10
0x00011C230PADCONFIG140 U2ECAP0_IN_APWM_OUTSYNC0_OUTCPTS0_RFT_CLKSPI2_CS3I3C0_SDAPULLENSPI7_CS0GPIO1_11
0x00011C234PADCONFIG141 U3EXT_REFCLK1SYNC1_OUTSPI7_CLKGPIO1_12
0x00011C238PADCONFIG142 V6TIMER_IO0ECAP1_IN_APWM_OUTSYSCLKOUT0SPI7_D0GPIO1_13BOOTMODE4
0x00011C23CPADCONFIG143 V5TIMER_IO1ECAP2_IN_APWM_OUTOBSCLK0SPI7_D1GPIO1_14BOOTMODE5
0x00011C240PADCONFIG144 R26MMC1_DAT3UART7_RXDGPIO1_15
0x00011C244PADCONFIG145 R25MMC1_DAT2UART7_TXDGPIO1_16
0x00011C248PADCONFIG146 P24MMC1_DAT1UART7_CTSnECAP0_IN_APWM_OUTTIMER_IO0UART4_RXDGPIO1_17
0x00011C24CPADCONFIG147 R24MMC1_DAT0UART7_RTSnECAP1_IN_APWM_OUTTIMER_IO1UART4_TXDGPIO1_18
0x00011C250PADCONFIG148 P25MMC1_CLKUART8_RXDI2C4_SCLGPIO1_19
0x00011C254PADCONFIG149 R29MMC1_CMDUART8_TXDI2C4_SDAGPIO1_20
0x00011C258PADCONFIG150 P23MMC1_SDCDUART8_CTSnUART0_DCDnTIMER_IO2EQEP2_IPCIE2_CLKREQnGPIO1_21PRG0_IEP0_EDC_LATCH_IN1
0x00011C25CPADCONFIG151 R28MMC1_SDWPUART8_RTSnUART0_DSRnTIMER_IO3ECAP2_IN_APWM_OUTEQEP2_SPCIE3_CLKREQnGPIO1_22PRG0_IEP0_EDC_SYNC_OUT1
0x00011C260PADCONFIG152 T28MMC2_DAT3UART9_RXDCPTS0_HW1TSPUSHI2C5_SCLGPIO1_23
0x00011C264PADCONFIG153 T29MMC2_DAT2UART9_TXDCPTS0_HW2TSPUSHI2C5_SDAGPIO1_24
0x00011C268PADCONFIG154 T27MMC2_DAT1UART9_CTSnUART0_DTRnTIMER_IO4UART6_RXDEQEP2_AGPIO1_25PRG0_IEP1_EDC_LATCH_IN1
0x00011C26CPADCONFIG155 T24MMC2_DAT0UART9_RTSnUART0_RInTIMER_IO5UART6_TXDEQEP2_BGPIO1_26PRG0_IEP1_EDC_SYNC_OUT1
0x00011C270PADCONFIG156 T26MMC2_CLKUSB0_DRVVBUSUSB1_DRVVBUSTIMER_IO6I2C3_SCLUART3_RXDGPIO1_27
0x00011C274PADCONFIG157 T25MMC2_CMDUSB0_DRVVBUSUSB1_DRVVBUSTIMER_IO7I2C3_SDAUART3_TXDGPIO1_28
0x00011C278PADCONFIG158 T6RESETSTATz
0x00011C27CPADCONFIG159 U1PORz_OUT
0x00011C280PADCONFIG160 U4SOC_SAFETY_ERRORn
0x00011C284PADCONFIG161 V1TDI
0x00011C288PADCONFIG162 V3TDO
0x00011C28CPADCONFIG163 V2TMS
0x04301C000WKUP_PADCONFIG0 E20MCU_OSPI0_CLKMCU_HYPERBUS0_CKWKUP_GPIO0_16
0x04301C004WKUP_PADCONFIG1 C21MCU_OSPI0_LBCLKOMCU_HYPERBUS0_CKnWKUP_GPIO0_17
0x04301C008WKUP_PADCONFIG2 D21MCU_OSPI0_DQSMCU_HYPERBUS0_RWDSWKUP_GPIO0_18
0x04301C00CWKUP_PADCONFIG3 D20MCU_OSPI0_D0MCU_HYPERBUS0_DQ0WKUP_GPIO0_19
0x04301C010WKUP_PADCONFIG4 G19MCU_OSPI0_D1MCU_HYPERBUS0_DQ1WKUP_GPIO0_20
0x04301C014WKUP_PADCONFIG5 G20MCU_OSPI0_D2MCU_HYPERBUS0_DQ2WKUP_GPIO0_21
0x04301C018WKUP_PADCONFIG6 F20MCU_OSPI0_D3MCU_HYPERBUS0_DQ3WKUP_GPIO0_22
0x04301C01CWKUP_PADCONFIG7 F21MCU_OSPI0_D4MCU_HYPERBUS0_DQ4WKUP_GPIO0_23
0x04301C020WKUP_PADCONFIG8 E21MCU_OSPI0_D5MCU_HYPERBUS0_DQ5WKUP_GPIO0_24
0x04301C024WKUP_PADCONFIG9 B22MCU_OSPI0_D6MCU_HYPERBUS0_DQ6WKUP_GPIO0_25
0x04301C028WKUP_PADCONFIG10 G21MCU_OSPI0_D7MCU_HYPERBUS0_DQ7WKUP_GPIO0_26
0x04301C02CWKUP_PADCONFIG11 F19MCU_OSPI0_CSn0MCU_HYPERBUS0_CSn0WKUP_GPIO0_27
0x04301C030WKUP_PADCONFIG12 E19MCU_OSPI0_CSn1MCU_HYPERBUS0_RESETnWKUP_GPIO0_28
0x04301C034WKUP_PADCONFIG13 F22MCU_OSPI1_CLKWKUP_GPIO0_29
0x04301C038WKUP_PADCONFIG14 A23MCU_OSPI1_LBCLKOMCU_OSPI0_CSn2MCU_HYPERBUS0_RESETOnMCU_OSPI0_RESET_OUT0WKUP_GPIO0_30
0x04301C03CWKUP_PADCONFIG15 B23MCU_OSPI1_DQSMCU_OSPI0_CSn3MCU_HYPERBUS0_INTnMCU_OSPI0_ECC_FAILWKUP_GPIO0_31
0x04301C040WKUP_PADCONFIG16 D22MCU_OSPI1_D0WKUP_GPIO0_32
0x04301C044WKUP_PADCONFIG17 G22MCU_OSPI1_D1MCU_UART0_RXDMCU_SPI1_CS1WKUP_GPIO0_33
0x04301C048WKUP_PADCONFIG18 D23MCU_OSPI1_D2MCU_UART0_TXDMCU_SPI1_CS2WKUP_GPIO0_34
0x04301C04CWKUP_PADCONFIG19 C23MCU_OSPI1_D3MCU_UART0_CTSnMCU_SPI0_CS1WKUP_GPIO0_35
0x04301C050WKUP_PADCONFIG20 C22MCU_OSPI1_CSn0WKUP_GPIO0_36
0x04301C054WKUP_PADCONFIG21 E22MCU_OSPI1_CSn1MCU_HYPERBUS0_WPnMCU_TIMER_IO0MCU_HYPERBUS0_CSn1MCU_UART0_RTSnMCU_SPI0_CS2MCU_OSPI0_RESET_OUT1WKUP_GPIO0_37
0x04301C058WKUP_PADCONFIG22 B27MCU_RGMII1_TX_CTLMCU_RMII1_CRS_DVWKUP_GPIO0_38
0x04301C05CWKUP_PADCONFIG23 C25MCU_RGMII1_RX_CTLMCU_RMII1_RX_ERWKUP_GPIO0_39
0x04301C060WKUP_PADCONFIG24 A28MCU_RGMII1_TD3MCU_TIMER_IO2MCU_ADC_EXT_TRIGGER0WKUP_GPIO0_40
0x04301C064WKUP_PADCONFIG25 A27MCU_RGMII1_TD2MCU_TIMER_IO3MCU_ADC_EXT_TRIGGER1WKUP_GPIO0_41
0x04301C068WKUP_PADCONFIG26 A26MCU_RGMII1_TD1MCU_RMII1_TXD1WKUP_GPIO0_42
0x04301C06CWKUP_PADCONFIG27 B25MCU_RGMII1_TD0MCU_RMII1_TXD0WKUP_GPIO0_43
0x04301C070WKUP_PADCONFIG28 B26MCU_RGMII1_TXCMCU_RMII1_TX_ENWKUP_GPIO0_44
0x04301C074WKUP_PADCONFIG29 C24MCU_RGMII1_RXCMCU_RMII1_REF_CLKWKUP_GPIO0_45
0x04301C078WKUP_PADCONFIG30 A25MCU_RGMII1_RD3MCU_TIMER_IO4WKUP_GPIO0_46
0x04301C07CWKUP_PADCONFIG31 D24MCU_RGMII1_RD2MCU_TIMER_IO5WKUP_GPIO0_47
0x04301C080WKUP_PADCONFIG32 A24MCU_RGMII1_RD1MCU_RMII1_RXD1WKUP_GPIO0_48
0x04301C084WKUP_PADCONFIG33 B24MCU_RGMII1_RD0MCU_RMII1_RXD0WKUP_GPIO0_49
0x04301C088WKUP_PADCONFIG34 E23MCU_MDIO0_MDIOWKUP_GPIO0_50
0x04301C08CWKUP_PADCONFIG35 F23MCU_MDIO0_MDCWKUP_GPIO0_51
0x04301C090WKUP_PADCONFIG36 E27MCU_SPI0_CLKWKUP_GPIO0_52MCU_BOOTMODE00
0x04301C094WKUP_PADCONFIG37 E24MCU_SPI0_D0WKUP_GPIO0_53MCU_BOOTMODE01
0x04301C098WKUP_PADCONFIG38 E28MCU_SPI0_D1MCU_TIMER_IO0WKUP_GPIO0_54MCU_BOOTMODE02
0x04301C09CWKUP_PADCONFIG39 E25MCU_SPI0_CS0MCU_TIMER_IO1WKUP_GPIO0_55
0x04301C0A0WKUP_PADCONFIG40 J29WKUP_UART0_RXDWKUP_GPIO0_56
0x04301C0A4WKUP_PADCONFIG41 J28WKUP_UART0_TXDWKUP_GPIO0_57
0x04301C0A8WKUP_PADCONFIG42 D29MCU_MCAN0_TXWKUP_GPIO0_58
0x04301C0ACWKUP_PADCONFIG43 C29MCU_MCAN0_RXWKUP_GPIO0_59
0x04301C0B0WKUP_PADCONFIG44 F26MCU_SPI1_CLKMCU_SPI1_CLKWKUP_GPIO0_0MCU_BOOTMODE03
0x04301C0B4WKUP_PADCONFIG45 F25MCU_SPI1_D0MCU_SPI1_D0WKUP_GPIO0_1MCU_BOOTMODE04
0x04301C0B8WKUP_PADCONFIG46 F28MCU_SPI1_D1MCU_SPI1_D1WKUP_GPIO0_2MCU_BOOTMODE05
0x04301C0BCWKUP_PADCONFIG47 F27MCU_SPI1_CS0MCU_SPI1_CS0WKUP_GPIO0_3
0x04301C0C0WKUP_PADCONFIG48 G25MCU_MCAN1_TXMCU_MCAN1_TXMCU_SPI0_CS3MCU_ADC_EXT_TRIGGER0WKUP_GPIO0_4
0x04301C0C4WKUP_PADCONFIG49 G24MCU_MCAN1_RXMCU_MCAN1_RXMCU_SPI1_CS3MCU_ADC_EXT_TRIGGER1WKUP_GPIO0_5
0x04301C0C8WKUP_PADCONFIG50 F29WKUP_UART0_CTSnWKUP_UART0_CTSnMCU_CPTS0_HW1TSPUSHMCU_I2C1_SCLWKUP_GPIO0_6
0x04301C0CCWKUP_PADCONFIG51 G28WKUP_UART0_RTSnWKUP_UART0_RTSnMCU_CPTS0_HW2TSPUSHMCU_I2C1_SDAWKUP_GPIO0_7
0x04301C0D0WKUP_PADCONFIG52 G27MCU_I2C1_SCLMCU_I2C1_SCLMCU_CPTS0_TS_SYNCMCU_I3C1_SCLMCU_TIMER_IO6WKUP_GPIO0_8
0x04301C0D4WKUP_PADCONFIG53 G26MCU_I2C1_SDAMCU_I2C1_SDAMCU_CPTS0_TS_COMPMCU_I3C1_SDAMCU_TIMER_IO7WKUP_GPIO0_9
0x04301C0D8WKUP_PADCONFIG54 H26MCU_EXT_REFCLK0MCU_EXT_REFCLK0MCU_UART0_TXDMCU_ADC_EXT_TRIGGER0MCU_CPTS0_RFT_CLKMCU_SYSCLKOUT0WKUP_GPIO0_10
0x04301C0DCWKUP_PADCONFIG55 H27MCU_OBSCLK0MCU_OBSCLK0MCU_UART0_RXDMCU_ADC_EXT_TRIGGER1MCU_TIMER_IO1MCU_I3C1_SDAPULLENMCU_CLKOUT0WKUP_GPIO0_11
0x04301C0E0WKUP_PADCONFIG56 G29MCU_UART0_TXDMCU_SPI0_CS1WKUP_GPIO0_12MCU_BOOTMODE08
0x04301C0E4WKUP_PADCONFIG57 H28MCU_UART0_RXDMCU_SPI1_CS1WKUP_GPIO0_13MCU_BOOTMODE09
0x04301C0E8WKUP_PADCONFIG58 H29MCU_UART0_CTSnMCU_SPI0_CS2WKUP_GPIO0_14MCU_BOOTMODE06
0x04301C0ECWKUP_PADCONFIG59 J27MCU_UART0_RTSnMCU_SPI1_CS2WKUP_GPIO0_15MCU_BOOTMODE07
0x04301C0F0WKUP_PADCONFIG60 D26MCU_I3C0_SCLMCU_UART0_CTSnMCU_TIMER_IO8WKUP_GPIO0_60
0x04301C0F4WKUP_PADCONFIG61 D25MCU_I3C0_SDAMCU_UART0_RTSnMCU_TIMER_IO9WKUP_GPIO0_61
0x04301C0F8WKUP_PADCONFIG62 J25WKUP_I2C0_SCLWKUP_GPIO0_62
0x04301C0FCWKUP_PADCONFIG63 H24WKUP_I2C0_SDAWKUP_GPIO0_63
0x04301C100WKUP_PADCONFIG64 J26MCU_I2C0_SCLWKUP_GPIO0_64
0x04301C104WKUP_PADCONFIG65 H25MCU_I2C0_SDAWKUP_GPIO0_65
0x04301C108WKUP_PADCONFIG66 E26MCU_I3C0_SDAPULLENWKUP_GPIO0_66
0x04301C10CWKUP_PADCONFIG67 G23PMIC_POWER_EN1MCU_I3C1_SDAPULLENWKUP_GPIO0_67
0x04301C110WKUP_PADCONFIG68 D27MCU_SAFETY_ERRORn
0x04301C114WKUP_PADCONFIG69 D28MCU_RESETz
0x04301C118WKUP_PADCONFIG70 C27MCU_RESETSTATz
0x04301C11CWKUP_PADCONFIG71 B28MCU_PORz_OUT
0x04301C120WKUP_PADCONFIG72 E29TCK
0x04301C124WKUP_PADCONFIG73 F24TRSTn
0x04301C128WKUP_PADCONFIG74 C26EMU0
0x04301C12CWKUP_PADCONFIG75 B29EMU1
0x04301C130WKUP_PADCONFIG76 K25MCU_ADC0_AIN0
0x04301C134WKUP_PADCONFIG77 K26MCU_ADC0_AIN1
0x04301C138WKUP_PADCONFIG78 K28MCU_ADC0_AIN2
0x04301C13CWKUP_PADCONFIG79 L28MCU_ADC0_AIN3
0x04301C140WKUP_PADCONFIG80 K24MCU_ADC0_AIN4
0x04301C144WKUP_PADCONFIG81 K27MCU_ADC0_AIN5
0x04301C148WKUP_PADCONFIG82 K29MCU_ADC0_AIN6
0x04301C14CWKUP_PADCONFIG83 L29MCU_ADC0_AIN7
0x04301C150WKUP_PADCONFIG84 N23MCU_ADC1_AIN0
0x04301C154WKUP_PADCONFIG85 M25MCU_ADC1_AIN1
0x04301C158WKUP_PADCONFIG86 L24MCU_ADC1_AIN2
0x04301C15CWKUP_PADCONFIG87 L26MCU_ADC1_AIN3
0x04301C160WKUP_PADCONFIG88 N24MCU_ADC1_AIN4
0x04301C164WKUP_PADCONFIG89 M24MCU_ADC1_AIN5
0x04301C168WKUP_PADCONFIG90 L25MCU_ADC1_AIN6
0x04301C16CWKUP_PADCONFIG91 L27MCU_ADC1_AIN7
0x04301C170WKUP_PADCONFIG92 C28RESET_REQz
0x04301C174WKUP_PADCONFIG93 J24PORz