JAJSIF7K September 2021 – April 2024 TDA4VM , TDA4VM-Q1
PRODUCTION DATA
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Table 6-83, Figure 6-94, Table 6-84, and Figure 6-95 present timing requirements and switching characteristics for MMC0 – High Speed DDR Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
HSDDR1 | tsu(cmdV-clkH) | Setup time, MMC0_CMD valid before MMC0_CLK rising edge | 2 | ns | |
HSDDR2 | th(clkH-cmdV) | Hold time, MMC0_CMD valid after MMC0_CLK rising edge | 2.5 | ns | |
HSDDR3 | tsu(dV-clkV) | Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition | 0.74 | ns | |
HSDDR4 | th(clkV-dV) | Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition | 1.67 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC0_CLK | 50 | MHz | ||
HSDDR5 | tc(clk) | Cycle time, MMC0_CLK | 20 | ns | |
HSDDR6 | tw(clkH) | Pulse duration, MMC0_CLK high | 9.2 | ns | |
HSDDR7 | tw(clkL) | Pulse duration, MMC0_CLK low | 9.2 | ns | |
HSDDR8 | td(clkH-cmdV) | Delay time, MMC0_CLK rising edge to MMC0_CMD transition | 3.4 | 9.72 | ns |
HSDDR9 | td(clkV-dV) | Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition | 2.9 | 6.6 | ns |