JAJSIF7 データシート

JAJSIF7K September 2021 – April 2024 TDA4VM , TDA4VM-Q1

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

ALF|827

サーマルパッド・メカニカル・データ

発注情報

6.9.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode

NO.			MODE⁽⁷⁾	MAX	UNIT
FA5⁽¹⁾	t_acc(d)	Data access time	div_by_1_mode	H⁽⁵⁾	ns
FA20⁽²⁾	t_{acc1-pgmode(d)}	Page mode successive data access time	div_by_1_mode	P⁽⁴⁾	ns
FA21⁽³⁾	t_{acc2-pgmode(d)}	Page mode first data access time	div_by_1_mode	H⁽⁵⁾	ns

(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field.

(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾

(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾

(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(7) For div_by_1_mode:

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
- GPMC_CLK frequency = GPMC_FCLK frequency