JAJSLG1A april 2021 – february 2023 TDES954
PRODUCTION DATA
Receiver port control register assigns rules for lock and pass in the general status register and allows for enabling and disabling each Rx port.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7:6 | RESERVED | R | 0x2 | Reserved |
| 5:4 | PASS_SEL | R/W | 0x00 | Pass Output Select Both receivers can be active at the same time. This field controls the source of the PASS output. 00: Port 0 Receiver Pass 01: Port 1 Receiver Pass 10: Any Enabled Receiver Port Pass 11: All Enabled Receiver Ports Pass This field can only be written via a local I2C controller. |
| 3:2 | LOCK_SEL | R/W | 0x0 | Lock Output Select Both receivers can be active at the same time. This field controls the source of the LOCK output. 00: Port 0 Receiver Lock 01: Port 1 Receiver Lock 10: Any Enabled Receiver Port Lock 11: All Enabled Receiver Ports Lock. This field can only be written via a local I2C controller. |
| 1 | PORT1_EN | R/W | 0x1 | Port 1 Receiver Enable 0: Disable Port 1 Receiver 1: Enable Port 1 Receiver |
| 0 | PORT0_EN | R/W | 0x1 | Port 0 Receiver Enable 0: Disable Port 0 Receiver 1: Enable Port 0 Receiver |