JAJSLG1 データシート

JAJSLG1A april 2021 – february 2023 TDES954

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGZ|48
- MPQF123F

サーマルパッド・メカニカル・データ

RGZ|48
- QFND014T

発注情報

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER		TEST CONDITIONS		PIN OR FREQUENCY	MIN	TYP	MAX	UNIT
TOTAL POWER CONSUMPTION
P_T	Total power consumption for MIPI CSI-2 output mode, normal operation	2 x V³Link Input, V³Link line-rate = 4.0 Gbps CSI-2 line-rate = 1.6 Gbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL = LOW, default registers		V_(VDD18)= 1.89 V, V_(VDDIO) = 3.6 V		473	564	mW
P_T		2 x V³Link Input, V³Link line-rate = 4.0 Gbps CSI-2 line-rate = 1.6 Gbps, CS-I2 = 4 DATA lanes + 1 CLK lane VDD_SEL = HIGH, default registers		V_(VDD18)= 1.89 V, V_(VDD11) = 1.155 V V_(VDDIO) = 3.6 V			450	mW
DESERIALIZER SUPPLY CURRENT - V³Link Rx Port0 AND Rx Port1 PAIRED WITH 2x TSER953
I_DD-R2T4	Deserializer supply current 2 Rx 4 Tx	2 x V³Link Input, V³Link line-rate = 4.0 Gbps per Rx port CSI-2 line-rate = 1.6 Gbps per lane, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=LOW, default registers, includes CSI-2 load current		VDD18		240	279	mA
				VDDIO		5	10	mA
		2 x V³Link Input, V³Link line-rate = 4.0 Gbps per Rx port CSI-2 line-rate = 1.6 Gbps per lane, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=HIGH, default registers, includes CSI-2 load current		VDD18		110	140	mA
				VDD11		100	130
				VDDIO		5	10
I_DD-R2T22	Deserializer supply current 2 Rx 2x2 Tx	2 x V³Link Input, V³Link line-rate = 4.0 Gbps per Rx port CSI-2 line-rate = 1.6 Gbps, Replicate mode, CSI-2 = 2x 2 DATA lanes and 2x 1 CLK lanes VDD_SEL=LOW, includes CSI-2 load current		VDD18		240	279	mA
				VDDIO		5	10	mA
		2 x V³Link Input, V³Link line-rate = 4.0 Gbps per Rx port CSI-2 line-rate = 1.6 Gbps, Replicate mode, CSI-2 = 2x 2 DATA lanes and 2x 1 CLK lanes VDD_SEL=HIGH , includes CSI-2 load current		VDD18		110	140	mA
				VDD11		100	130
				VDDIO		5	10
DESERIALIZER SUPPLY CURRENT - V³Link Rx Port0 OR Rx Port1 PAIRED WITH 1x TSER953
I_DD-R1T4	Deserializer supply current 1 Rx 4 Tx	1 x V³Link Input, V³Link line-rate = 4.0 Gbps CSI-2 line-rate = 800 Mbps per lane, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=LOW, default registers, includes CSI-2 load current		VDD18		170	188	mA
				VDDIO		5	10	mA
		1 x V³Link Input, V³Link line-rate = 4.0 Gbps CSI-2 line-rate = 800 Mbps per lane, CSI2 = 4 DATA lanes + 1 CLK lane VDD_SEL=HIGH, default registers, includes CSI-2 load current		VDD18		65	80	mA
				VDD11		80	100
				VDDIO		5	10
DESERIALIZER SUPPLY CURRENT - V³Link Rx Port0 AND Rx Port1 PAIRED WITH 2x DVP Mode Serializers
I_DD2-R2T4	Deserializer supply current 2G 2 Rx 4 Tx	2 x V³Link Input, V³Link line-rate = 1.867 Gbps per Rx port CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lanes VDD_SEL=LOW, includes CSI-2 load current		VDD18		220	265	mA
				VDDIO		5	10	mA
		2 x V³Link Input, V³Link line-rate = 1.867 Gbps per Rx port CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lanes VDD_SEL=HIGH, includes CSI-2 load current		VDD18		110	148	mA
				VDD11		85	100
				VDDIO		5	10
DESERIALIZER SUPPLY CURRENT - V³Link Rx Port0 OR Rx Port1 PAIRED WITH 1x DVP Mode Serializer
I_DD2-R1T4	Deserializer supply current 2G 1 Rx 4 Tx	1 x V³Link Input, V³Link line-rate = 1.867 Gbps CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=LOW, includes CSI-2 load current		VDD18		150	205	mA
				VDDIO		5	10	mA
		1 x V³Link Input, V³Link line-rate = 1.867 Gbps CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA lanes + 1 CLK lane VDD_SEL=HIGH, includes CSI-2 load current		VDD18		65	86	mA
				VDD11		75	110
				VDDIO		5	10
DESERIALIZER SUPPLY CURRENT - Power Down
I_DDZ	Deserializer shutdown current	PDB = HIGH to LOW, VDD_SEL = LOW		VDD18		82	115	mA
		PDB = HIGH to LOW, VDD_SEL = LOW		VDIO		2.5	5
		PDB = HIGH to LOW, VDD_SEL = HIGH		VDD18		10	15
				VDD11		30	110
				VDDIO		2.5	5
1.8-V LVCMOS I/O
V_OH	High level output voltage	I_OH = –2 mA, V_(VDDIO) = 1.71 to 1.89 V; V_(VDDIO) = VDD18 ±50 mV		GPIO[6:4], GPIO[2:0], LOCK, PASS	V_(VDDIO) – 0.45		V_(VDDIO)	V
V_OL	Low level output voltage	I_OL = 2 mA, V_(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18 ±50 mV		GPIO[6:0], LOCK, PASS	GND		0.45	V
V_IH	High level input voltage	V_(VDDIO) = 1.71 to 1.89 V; V_(VDDIO) = VDD18 ±50 mV		GPIO[6:0], BISTEN	0.65 × V_(VDDIO)		V_(VDDIO)	V
V_IH	High level input voltage	V_(VDDIO) = 1.71 to 1.89 V; V_(VDDIO) = VDD18 ±50 mV		PDB, XIN/REFCLK, VDD_SEL	1.17		V_(VDDIO)	V
V_IL	Low level input voltage	V_(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18 ±50 mV		GPIO[6:0], BISTEN	GND		0.35 × V_(VDDIO)	V
V_IL	Low level input voltage	V_(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18 ±50 mV		PDB, XIN/REFCLK, VDD_SEL	GND		0.63	V
I_IH	Input high current	VIN = V_(VDDIO) = 1.71 to 1.89 V,	Internal pulldown enabled	GPIO[6:0], PDB, BISTEN	–100		100	μA
I_IH	Input high current	VIN = V_(VDDIO) = 1.71 to 1.89 V,	Internal pulldown disabled	GPIO[6:0], XIN/REFCLK, VDD_SEL	–20		30	μA
I_IL	Input low current	V_IN = 0V		GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN	–20		30	μA
I_OS	Output short circuit current	V_OUT = 0 V	V_OUT = 0 V			–25		mA
I_OZ	TRI-STATE Output Current	V_OUT = 0 V or V_DDIO, PDB = L	V_OUT = 0 V or V_DDIO, PDB = L		–25		25	μA
3.3-V LVCMOS I/O
V_OH	High level output voltage	I_OH = –4 mA, V_(VDDIO) = 3.0 to 3.6 V		GPIO[6:4], GPIO[2:0], LOCK, PASS	2.4		V_(VDDIO)	V
V_OL	Low level output voltage	I_OL = 4 mA, V_(VDDIO) = 3.0 to 3.6 V		GPIO[6:0], LOCK, PASS	GND		0.4	V
V_IH	High level input voltage	V_(VDDIO) = 3 to 3.6 V		GPIO[6:0], BISTEN	2		V_(VDDIO)	V
V_IH	High level input voltage	V_(VDDIO) = 3 to 3.6 V		PDB, XIN/REFCLK, VDD_SEL	1.17		V_(VDDIO)
V_IL	Low level input voltage	V_(VDDIO) = 3 to 3.6 V		GPIO[6:0], BISTEN	GND		0.8	V
V_IL	Low level input voltage	V_(VDDIO) = 3 to 3.6 V		PDB, XIN/REFCLK, VDD_SEL	GND		0.63
I_IH	Input high current	V_IN = 3 to 3.6 V, internal pulldown enabled		GPIO[6:0], PDB, BISTEN	–190		190	μA
I_IH	Input high current	V_IN = 3 to 3.6 V, internal pulldown disabled		GPIO[6:0], XIN/REFCLK, VDD_SEL	–20		30	μA
I_IL	Input low current	V_IN = 0 V		GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN	–20		30	μA
I_OS	Output short circuit current	V_OUT = 0 V		GPIO[7:0], LOCK, PASS		–40		mA
I_OZ	TRI-STATE output current	V_OUT = 0 V or V_(VDDIO), PDB = L		GPIO[7:0], LOCK, PASS	–25		35	μA
SERIAL CONTROL BUS1
V_IH	Input high level			I2C_SDA, I2C_SCL	0.7 × V_(I2C)		V_(I2C)	V
V_IL	Input low level				GND		0.3 × V_(I2C)	V
V_HY	Input hysteresis					50		mV
V_OL	Output low level	Standard-mode/Fast-mode I_OL = 3 mA			0		0.4	V
V_OL	Output low level	Fast-mode Plus I_OL = 20 mA			0		0.4	V
I_IH	Input high current	V_IN = V_(I2C)			–10		10	µA
I_IL	Input low current	V_IN = 0V			–10		10	µA
C_IN	Input capacitance					5		pF
V³LINK INPUT
V_CM	Common mode voltage			RIN0+, RIN0- RIN1+, RIN1-		1.2		V
R_T	Internal termination resistor	Single-ended		RIN0+, RIN1+	40	50	60	Ω
R_T	Internal termination resistor	Differential		RIN0+, RIN0- RIN1+, RIN1-	80	100	120	Ω
V³LINK BIDIRECTIONAL CONTROL CHANNEL
V_OUT-BC	Back Channel Output Single-ended voltage	RL = 50 Ω, coaxial configuration, forward channel disabled		RIN0+, RIN0- RIN1+, RIN1-	190	225	260	mV
V_OD-BC	Back channel output differential	RL = 100 Ω, STP configuration, forward channel disabled		RIN0+, RIN0- RIN1+, RIN1-	380	450	520	mV
HSTX DRIVER
V_CMTX	HS transmit static common-mode voltage			CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLK1P/N, CSI_CLK0P/N	150	200	250	mV
\|ΔV_CMTX(1,0)\|	VCMTX mismatch when output is 1 or 0						5	mV_P-P
\|V_OD\|	HS transmit differential voltage				140	200	270	mV
\|ΔV_OD\|	VOD mismatch when output is 1 or 0						14	mV
V_OHHS	HS output high voltage						360	mV
Z_OS	Single-ended output impedance				40	50	62.5	Ω
ΔZ_OS	Mismatch in single-ended output impedance						10	%
LPTX DRIVER
V_OH	High level output voltage	Applicable when the supported data rate is ≤ 1.5 Gbps		CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N, CSI_CLK1P/N, CSI_CLK0P/N	1.1	1.2	1.3	V
V_OH	High level output voltage	Applicable when the supported data rate is > 1.5 Gbps			0.95		1.3	V
V_OL	Low level output voltage				-50		50	mV
Z_OLP	Output impedance				110			Ω

(1) V_(VDDIO) = 1.8 V ± 5% OR 3.3 V ± 10%