JAJSLG1A april   2021  – february 2023 TDES954

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics CSI-2
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  RX MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Crystal Recommendations
      6. 7.4.6  Receiver Port Control
        1. 7.4.6.1 Video Stream Forwarding
      7. 7.4.7  LOCK and PASS Status
      8. 7.4.8  Input Jitter Tolerance
      9. 7.4.9  Adaptive Equalizer
        1. 7.4.9.1 Adaptive Equalizer Algorithm
        2. 7.4.9.2 AEQ Settings
          1. 7.4.9.2.1 AEQ Start-Up and Initialization
          2. 7.4.9.2.2 AEQ Range
          3. 7.4.9.2.3 AEQ Timing
          4. 7.4.9.2.4 AEQ Threshold
      10. 7.4.10 Channel Monitor Loop-Through Output Driver (CMLOUT)
        1. 7.4.10.1 Code Example for CMLOUT V3Link RX Port 0:
      11. 7.4.11 RX Port Status
        1. 7.4.11.1 RX Parity Status
        2. 7.4.11.2 V3Link Decoder Status
        3. 7.4.11.3 RX Port Input Signal Detection
        4. 7.4.11.4 Line Counter
        5. 7.4.11.5 Line Length
      12. 7.4.12 Sensor Status
      13. 7.4.13 GPIO Support
        1. 7.4.13.1 GPIO Input Control and Status
        2. 7.4.13.2 GPIO Output Pin Control
        3. 7.4.13.3 Forward Channel GPIO
        4. 7.4.13.4 Back Channel GPIO
        5. 7.4.13.5 Other GPIO Pin Controls
      14. 7.4.14 Line Valid and Frame Valid Indicators
      15. 7.4.15 CSI-2 Protocol Layer
      16. 7.4.16 CSI-2 Short Packet
      17. 7.4.17 CSI-2 Long Packet
      18. 7.4.18 CSI-2 Data Type Identifier
      19. 7.4.19 Virtual Channel and Context
      20. 7.4.20 CSI-2 Input Mode Virtual Channel Mapping
        1. 7.4.20.1 Example 1
        2. 7.4.20.2 Example 2:
      21. 7.4.21 CSI-2 Transmitter Frequency
      22. 7.4.22 CSI-2 Replicate Mode
      23. 7.4.23 CSI-2 Transmitter Output Control
      24. 7.4.24 CSI-2 Transmitter Status
      25. 7.4.25 Video Buffers
      26. 7.4.26 CSI-2 Line Count and Line Length
      27. 7.4.27 FrameSync Operation
        1. 7.4.27.1 External FrameSync Control
        2. 7.4.27.2 Internally Generated FrameSync
          1. 7.4.27.2.1 Code Example for Internally Generated FrameSync
      28. 7.4.28 CSI-2 Forwarding
        1. 7.4.28.1 Enabling and Disabling the CSI-2 Transmitter
        2. 7.4.28.2 Best-Effort Round Robin CSI-2 Forwarding
        3. 7.4.28.3 Synchronized Forwarding
        4. 7.4.28.4 Basic Synchronized Forwarding
          1. 7.4.28.4.1 Code Example for Basic Synchronized Forwarding
        5. 7.4.28.5 Line-Interleave Forwarding
          1. 7.4.28.5.1 Code Example for Line-Interleave Forwarding
        6. 7.4.28.6 Line-Concatenated Forwarding
          1. 7.4.28.6.1 Code Example for Line-Concatenate Forwarding
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus and Bidirectional Control Channel
        1. 7.5.1.1 Bidirectional Control
        2. 7.5.1.2 Device Address
        3. 7.5.1.3 Basic I2C Serial Bus Operation
      2. 7.5.2  I2C Target Operation
      3. 7.5.3  Remote Target Operation
        1. 7.5.3.1 Remote I2C Targets Data Throughput
      4. 7.5.4  Remote Target Addressing
      5. 7.5.5  Broadcast Write to Remote Target Devices
        1. 7.5.5.1 Code Example for Broadcast Write
      6. 7.5.6  I2C Controller Proxy
      7. 7.5.7  I2C Controller Proxy Timing
        1. 7.5.7.1 Code Example for Configuring Fast Mode Plus I2C Operation
      8. 7.5.8  Interrupt Support
        1. 7.5.8.1 Code Example to Enable Interrupts
        2. 7.5.8.2 V3Link Receive Port Interrupts
          1. 7.5.8.2.1 Interrupts on Forward Channel GPIO
          2. 7.5.8.2.2 Interrupts on Change in Sensor Status
        3. 7.5.8.3 Code Example to Readback Interrupts
        4. 7.5.8.4 CSI-2 Transmit Port Interrupts
      9. 7.5.9  Error Handling
        1. 7.5.9.1 Receive Frame Threshold
        2. 7.5.9.2 Port PASS Control
      10. 7.5.10 Timestamp – Video Skew Detection
      11. 7.5.11 Pattern Generation
        1. 7.5.11.1 Reference Color Bar Pattern
        2. 7.5.11.2 Fixed Color Patterns
        3. 7.5.11.3 Packet Generator Programming
          1. 7.5.11.3.1 Determining Color Bar Size
        4. 7.5.11.4 Code Example for Pattern Generator
      12. 7.5.12 V3Link BIST Mode
        1. 7.5.12.1 BIST Operation Through BISTEN Pin
        2. 7.5.12.2 BIST Operation Through Register Control
    6. 7.6 Register Maps
      1. 7.6.1   I2C Device ID Register
      2. 7.6.2   Reset Register
      3. 7.6.3   General Configuration Register
      4. 7.6.4   Revision/Mask ID Register
      5. 7.6.5   DEVICE_STS Register
      6. 7.6.6   PAR_ERR_THOLD_HI Register
      7. 7.6.7   PAR_ERR_THOLD_LO Register
      8. 7.6.8   BCC Watchdog Control Register
      9. 7.6.9   I2C Control 1 Register
      10. 7.6.10  I2C Control 2 Register
      11. 7.6.11  SCL High Time Register
      12. 7.6.12  SCL Low Time Register
      13. 7.6.13  RX_PORT_CTL Register
      14. 7.6.14  IO_CTL Register
      15. 7.6.15  GPIO_PIN_STS Register
      16. 7.6.16  GPIO_INPUT_CTL Register
      17. 7.6.17  GPIO0_PIN_CTL Register
      18. 7.6.18  GPIO1_PIN_CTL Register
      19. 7.6.19  GPIO2_PIN_CTL Register
      20. 7.6.20  GPIO3_PIN_CTL Register
      21. 7.6.21  GPIO4_PIN_CTL Register
      22. 7.6.22  GPIO5_PIN_CTL Register
      23. 7.6.23  GPIO6_PIN_CTL Register
      24. 7.6.24  RESERVED Register
      25. 7.6.25  FS_CTL Register
      26. 7.6.26  FS_HIGH_TIME_1 Register
      27. 7.6.27  FS_HIGH_TIME_0 Register
      28. 7.6.28  FS_LOW_TIME_1 Register
      29. 7.6.29  FS_LOW_TIME_0 Register
      30. 7.6.30  MAX_FRM_HI Register
      31. 7.6.31  MAX_FRM_LO Register
      32. 7.6.32  CSI_PLL_CTL Register
      33. 7.6.33  FWD_CTL1 Register
      34. 7.6.34  FWD_CTL2 Register
      35. 7.6.35  FWD_STS Register
      36. 7.6.36  INTERRUPT_CTL Register
      37. 7.6.37  INTERRUPT_STS Register
      38. 7.6.38  TS_CONFIG Register
      39. 7.6.39  TS_CONTROL Register
      40. 7.6.40  TS_LINE_HI Register
      41. 7.6.41  TS_LINE_LO Register
      42. 7.6.42  TS_STATUS Register
      43. 7.6.43  TIMESTAMP_P0_HI Register
      44. 7.6.44  TIMESTAMP_P0_LO Register
      45. 7.6.45  TIMESTAMP_P1_HI Register
      46. 7.6.46  TIMESTAMP_P1_LO Register
      47. 7.6.47  RESERVED Register
      48. 7.6.48  CSI_CTL Register
      49. 7.6.49  CSI_CTL2 Register
      50. 7.6.50  CSI_STS Register
      51. 7.6.51  CSI_TX_ICR Register
      52. 7.6.52  CSI_TX_ISR Register
      53. 7.6.53  CSI_TEST_CTL Register
      54. 7.6.54  CSI_TEST_PATT_HI Register
      55. 7.6.55  CSI_TEST_PATT_LO Register
      56. 7.6.56  RESERVED Register
      57. 7.6.57  RESERVED Register
      58. 7.6.58  RESERVED Register
      59. 7.6.59  RESERVED Register
      60. 7.6.60  RESERVED Register
      61. 7.6.61  RESERVED Register
      62. 7.6.62  SFILTER_CFG Register
      63. 7.6.63  AEQ_CTL1 Register
      64. 7.6.64  AEQ_ERR_THOLD Register
      65. 7.6.65  RESERVED Register
      66. 7.6.66  V3LINK_CAP Register
      67. 7.6.67  RAW_EMBED_DTYPE Register
      68. 7.6.68  V3LINK_PORT_SEL Register
      69. 7.6.69  RX_PORT_STS1 Register
      70. 7.6.70  RX_PORT_STS2 Register
      71. 7.6.71  RX_FREQ_HIGH Register
      72. 7.6.72  RX_FREQ_LOW Register
      73. 7.6.73  SENSOR_STS_0 Register
      74. 7.6.74  SENSOR_STS_1 Register
      75. 7.6.75  SENSOR_STS_2 Register
      76. 7.6.76  SENSOR_STS_3 Register
      77. 7.6.77  RX_PAR_ERR_HI Register
      78. 7.6.78  RX_PAR_ERR_LO Register
      79. 7.6.79  BIST_ERR_COUNT Register
      80. 7.6.80  BCC_CONFIG Register
      81. 7.6.81  DATAPATH_CTL1 Register
      82. 7.6.82  DATAPATH_CTL2 Register
      83. 7.6.83  SER_ID Register
      84. 7.6.84  SER_ALIAS_ID Register
      85. 7.6.85  TargetID[0] Register
      86. 7.6.86  TargetID[1] Register
      87. 7.6.87  TargetID[2] Register
      88. 7.6.88  TargetID[3] Register
      89. 7.6.89  TargetID[4] Register
      90. 7.6.90  TargetID[5] Register
      91. 7.6.91  TargetID[6] Register
      92. 7.6.92  TargetID[7] Register
      93. 7.6.93  TargetAlias[0] Register
      94. 7.6.94  TargetAlias[1] Register
      95. 7.6.95  TargetAlias[2] Register
      96. 7.6.96  TargetAlias[3] Register
      97. 7.6.97  TargetAlias[4] Register
      98. 7.6.98  TargetAlias[5] Register
      99. 7.6.99  TargetAlias[6] Register
      100. 7.6.100 TargetAlias[7] Register
      101. 7.6.101 PORT_CONFIG Register
      102. 7.6.102 BC_GPIO_CTL0 Register
      103. 7.6.103 BC_GPIO_CTL1 Register
      104. 7.6.104 RAW10_ID Register
      105. 7.6.105 RAW12_ID Register
      106. 7.6.106 CSI_VC_MAP Register
      107. 7.6.107 LINE_COUNT_HI Register
      108. 7.6.108 LINE_COUNT_LO Register
      109. 7.6.109 LINE_LEN_1 Register
      110. 7.6.110 LINE_LEN_0 Register
      111. 7.6.111 FREQ_DET_CTL Register
      112. 7.6.112 MAILBOX_1 Register
      113. 7.6.113 MAILBOX_2 Register
      114. 7.6.114 CSI_RX_STS Register
      115. 7.6.115 CSI_ERR_COUNTER Register
      116. 7.6.116 PORT_CONFIG2 Register
      117. 7.6.117 PORT_PASS_CTL Register
      118. 7.6.118 SEN_INT_RISE_CTL Register
      119. 7.6.119 SEN_INT_FALL_CTL Register
      120. 7.6.120 RESERVED Register
      121. 7.6.121 REFCLK_FREQ Register
      122. 7.6.122 RESERVED Register
      123. 7.6.123 IND_ACC_CTL Register
      124. 7.6.124 IND_ACC_ADDR Register
      125. 7.6.125 IND_ACC_DATA Register
      126. 7.6.126 BIST Control Register
      127. 7.6.127 RESERVED Register
      128. 7.6.128 RESERVED Register
      129. 7.6.129 RESERVED Register
      130. 7.6.130 RESERVED Register
      131. 7.6.131 MODE_IDX_STS Register
      132. 7.6.132 LINK_ERROR_COUNT Register
      133. 7.6.133 V3LINK_ENC_CTL Register
      134. 7.6.134 RESERVED Register
      135. 7.6.135 FV_MIN_TIME Register
      136. 7.6.136 RESERVED Register
      137. 7.6.137 GPIO_PD_CTL Register
      138. 7.6.138 RESERVED Register
      139. 7.6.139 PORT_DEBUG Register
      140. 7.6.140 RESERVED Register
      141. 7.6.141 AEQ_CTL2 Register
      142. 7.6.142 AEQ_STATUS Register
      143. 7.6.143 ADAPTIVE EQ BYPASS Register
      144. 7.6.144 AEQ_MIN_MAX Register
      145. 7.6.145 RESERVED Register
      146. 7.6.146 RESERVED Register
      147. 7.6.147 PORT_ICR_HI Register
      148. 7.6.148 PORT_ICR_LO Register
      149. 7.6.149 PORT_ISR_HI Register
      150. 7.6.150 PORT_ISR_LO Register
      151. 7.6.151 FC_GPIO_STS Register
      152. 7.6.152 FC_GPIO_ICR Register
      153. 7.6.153 SEN_INT_RISE_STS Register
      154. 7.6.154 SEN_INT_FALL_STS Register
      155. 7.6.155 V3LINK_RX_ID0 Register
      156. 7.6.156 V3LINK_RX_ID1 Register
      157. 7.6.157 V3LINK_RX_ID2 Register
      158. 7.6.158 V3LINK_RX_ID3 Register
      159. 7.6.159 V3LINK_RX_ID4 Register
      160. 7.6.160 V3LINK_RX_ID5 Register
      161. 7.6.161 I2C_RX0_ID Register
      162. 7.6.162 I2C_RX1_ID Register
      163. 7.6.163 RESERVED Register
      164. 7.6.164 RESERVED Register
      165. 7.6.165 Indirect Access Registers
      166. 7.6.166 Reserved Register
      167. 7.6.167 PGEN_CTL Register
      168. 7.6.168 PGEN_CFG Register
      169. 7.6.169 PGEN_CSI_DI Register
      170. 7.6.170 PGEN_LINE_SIZE1 Register
      171. 7.6.171 PGEN_LINE_SIZE0 Register
      172. 7.6.172 PGEN_BAR_SIZE1 Register
      173. 7.6.173 PGEN_BAR_SIZE0 Register
      174. 7.6.174 PGEN_ACT_LPF1 Register
      175. 7.6.175 PGEN_ACT_LPF0 Register
      176. 7.6.176 PGEN_TOT_LPF1 Register
      177. 7.6.177 PGEN_TOT_LPF0 Register
      178. 7.6.178 PGEN_LINE_PD1 Register
      179. 7.6.179 PGEN_LINE_PD0 Register
      180. 7.6.180 PGEN_VBP Register
      181. 7.6.181 PGEN_VFP Register
      182. 7.6.182 PGEN_COLOR0 Register
      183. 7.6.183 PGEN_COLOR1 Register
      184. 7.6.184 PGEN_COLOR2 Register
      185. 7.6.185 PGEN_COLOR3 Register
      186. 7.6.186 PGEN_COLOR4 Register
      187. 7.6.187 PGEN_COLOR5 Register
      188. 7.6.188 PGEN_COLOR6 Register
      189. 7.6.189 PGEN_COLOR7 Register
      190. 7.6.190 PGEN_COLOR8 Register
      191. 7.6.191 PGEN_COLOR9 Register
      192. 7.6.192 PGEN_COLOR10 Register
      193. 7.6.193 PGEN_COLOR11 Register
      194. 7.6.194 PGEN_COLOR12 Register
      195. 7.6.195 PGEN_COLOR13 Register
      196. 7.6.196 PGEN_COLOR14 Register
      197. 7.6.197 RESERVED Register
      198. 7.6.198 CSI0_TCK_PREP Register
      199. 7.6.199 CSI0_TCK_ZERO Register
      200. 7.6.200 CSI0_TCK_TRAIL Register
      201. 7.6.201 CSI0_TCK_POST Register
      202. 7.6.202 CSI0_THS_PREP Register
      203. 7.6.203 CSI0_THS_ZERO Register
      204. 7.6.204 CSI0_THS_TRAIL Register
      205. 7.6.205 CSI0_THS_EXIT Register
      206. 7.6.206 CSI0_TPLX Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 System
      2. 8.1.2 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
    1. 9.1 VDD and VDDIO Power Supply
    2. 9.2 Power-Up Sequencing
      1. 9.2.1 PDB Pin
      2. 9.2.2 System Initialization
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
      1. 10.1.1 Ground
      2. 10.1.2 Routing V3Link Signal Traces and PoC Filter
      3. 10.1.3 Routing CSI-2 Signal Traces
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.4.9.2.3 AEQ Timing

The dwell time for AEQ to wait for lock or error free status is also programmable. When checking each EQ setting the AEQ will wait for a time interval, controlled by the ADAPTIVE_EQ_RELOCK_TIME field in the AEQ_CTL2 register (see Table 7-159) before incrementing to the next allowable EQ gain setting. The default wait time is set to 2.62 ms based on REFCLK = 25 MHz. Once the maximum setting is reached, if there is no lock acquired during the programmed relock time, the AEQ will restart adaption at the minimum setting or AEQ_FLOOR value.