JAJSLG2A
April 2021 – September 2023
TDES960
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
AC Electrical Characteristics
6.7
CSI-2 Timing Specifications
6.8
Recommended Timing for the Serial Control Bus
6.9
Timing Diagrams
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.1.1
Functional Description
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
7.4.1
CSI-2 Mode
7.4.2
RAW Mode
7.4.3
MODE Pin
7.4.4
REFCLK
7.4.5
Receiver Port Control
7.4.5.1
Video Stream Forwarding
7.4.6
Input Jitter Tolerance
7.4.7
Adaptive Equalizer
7.4.7.1
Channel Requirements
7.4.7.2
Adaptive Equalizer Algorithm
7.4.7.3
AEQ Settings
7.4.7.3.1
AEQ Start-Up and Initialization
7.4.7.3.2
AEQ Range
7.4.7.3.3
AEQ Timing
7.4.7.3.4
AEQ Threshold
7.4.8
Channel Monitor Loop-Through Output Driver
7.4.8.1
Code Example for CMLOUT V3LINK RX Port 0:
7.4.9
RX Port Status
7.4.9.1
RX Parity Status
7.4.9.2
V3Link Decoder Status
7.4.9.3
RX Port Input Signal Detection
7.4.9.4
Line Counter
7.4.9.5
Line Length
7.4.10
Sensor Status
7.4.11
GPIO Support
7.4.11.1
GPIO Input Control and Status
7.4.11.2
GPIO Output Pin Control
7.4.11.3
Forward Channel GPIO
7.4.11.4
Back Channel GPIO
7.4.11.5
GPIO Pin Status
7.4.11.6
Other GPIO Pin Controls
7.4.12
RAW Mode LV / FV Controls
7.4.13
CSI-2 Protocol Layer
7.4.14
CSI-2 Short Packet
7.4.15
CSI-2 Long Packet
7.4.16
CSI-2 Data Identifier
7.4.17
Virtual Channel and Context
7.4.18
CSI-2 Mode Virtual Channel Mapping
7.4.18.1
Example 1
7.4.18.2
Example 2
7.4.19
CSI-2 Transmitter Frequency
7.4.20
CSI-2 Output Bandwidth
7.4.20.1
CSI-2 Output Bandwidth Calculation Example
7.4.21
CSI-2 Transmitter Status
7.4.22
Video Buffers
7.4.23
CSI-2 Line Count and Line Length
7.4.24
FrameSync Operation
7.4.24.1
External FrameSync Control
7.4.24.2
Internally Generated FrameSync
7.4.24.2.1
Code Example for Internally Generated FrameSync
7.4.25
CSI-2 Forwarding
7.4.25.1
Best-Effort Round Robin CSI-2 Forwarding
7.4.25.2
Synchronized CSI-2 Forwarding
7.4.25.3
Basic Synchronized CSI-2 Forwarding
7.4.25.3.1
Code Example for Basic Synchronized CSI-2 Forwarding
7.4.25.4
Line-Interleaved CSI-2 Forwarding
7.4.25.4.1
Code Example for Line-Interleaved CSI-2 Forwarding
7.4.25.5
Line-Concatenated CSI-2 Forwarding
7.4.25.5.1
Code Example for Line-Concatenated CSI-2 Forwarding
7.4.25.6
CSI-2 Replicate Mode
7.4.25.7
CSI-2 Transmitter Output Control
7.4.25.8
Enabling and Disabling CSI-2 Transmitters
7.5
Programming
7.5.1
Serial Control Bus
7.5.2
Second I2C Port
7.5.3
I2C Target Operation
7.5.4
Remote Target Operation
7.5.5
Remote Target Addressing
7.5.6
Broadcast Write to Remote Devices
7.5.6.1
Code Example for Broadcast Write
7.5.7
I2C Controller Proxy
7.5.8
I2C Controller Proxy Timing
7.5.8.1
Code Example for Configuring Fast-Mode Plus I2C Operation
7.5.9
Interrupt Support
7.5.9.1
Code Example to Enable Interrupts
7.5.9.2
V3Link Receive Port Interrupts
7.5.9.3
Interrupts on Forward Channel GPIO
7.5.9.4
Interrupts on Change in Sensor Status
7.5.9.5
Code Example to Readback Interrupts
7.5.9.6
CSI-2 Transmit Port Interrupts
7.5.10
Error Handling
7.5.10.1
Receive Frame Threshold
7.5.10.2
Port PASS Control
7.5.11
Timestamp – Video Skew Detection
7.5.12
Pattern Generation
7.5.12.1
Reference Color Bar Pattern
7.5.12.2
Fixed Color Patterns
7.5.12.3
Pattern Generator Programming
7.5.12.3.1
Determining Color Bar Size
7.5.12.4
Code Example for Pattern Generator
7.5.13
V3Link BIST Mode
7.5.13.1
BIST Operation
7.6
Register Maps
7.6.1
Main Registers
7.6.2
Indirect Access Registers
7.6.2.1
PATGEN_And_CSI-2 Registers
8
Application and Implementation
8.1
Application Information
8.1.1
Power Over Coax
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
System Examples
8.4
Power Supply Recommendations
8.4.1
VDD Power Supply
8.4.2
Power-Up Sequencing
8.4.2.1
PDB Pin
8.4.2.2
System Initialization
8.5
Layout
8.5.1
Layout Guidelines
8.5.1.1
Ground
8.5.1.2
Routing V3Link Signal Traces and PoC Filter
8.5.1.3
CSI-2 Guidelines
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RTD|64
MPQF141C
サーマルパッド・メカニカル・データ
発注情報
jajslg2a_oa
6.9
Timing Diagrams
Figure 6-1
LVCMOS Transition Times
Figure 6-2
V
3
Link Receiver VID, VIN , VCM
Figure 6-3
Deserializer Data Lock Time
Figure 6-4
I2C Serial Control Bus Timing
Figure 6-5
Clock and Data Timing in HS Transmission
Figure 6-6
High Speed Data Transmission Burst
Figure 6-7
Switching the Clock Lane between Clock Transmission and Low-Power Mode
Figure 6-8
Long Line Packets and Short Frame Sync Packets
Figure 6-9
CSI-2 General Frame Format (Single Rx / VC)
Figure 6-10
4 MIPI Data Lane Configuration