JAJSLG2A April 2021 – September 2023 TDES960
PRODUCTION DATA
A valid 23-MHz to 26-MHz reference clock is required on the REFCLK pin 5 for precise frequency operation. The REFCLK frequency defines all internal clock timers, including the back channel rate, I2C timers, CSI-2 datarate, FrameSync signal parameters, and other timing critical internal circuitry. REFCLK input must be continuous. If the REFCLK input does not detect a transition more than 20 µs, this may cause a disruption in the CSI-2 output. REFCLK must be applied to the TDES960 only when the supply rails are above minimum levels (see Figure 8-18). At start-up, the TDES960 defaults to an internal oscillator to generate an backup internal reference clock at nominal frequency of 25 MHz ±10%.
As an option for mitigating EMI / EMC, the TDES960 is capable of tolerating a REFCLK with spread-spectrum clocking (SSC) profile with up to ±0.5% amplitude deviations (center spread) or up to 1% amplitude deviations (down spread) and up to 33-kHz frequency modulation from a clock source.
The REFCLK LVCMOS input oscillator specifications are listed in Table 7-2.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| REFERENCE CLOCK | ||||||
| Frequency tolerance with aging | –20°C ≤ TA ≤ 85°C, aging, no spread-spectrum | ±100 | ppm | |||
| Amplitude | 800 | 1200 | V(VDDIO) | mVp-p | ||
| Symmetry | Duty Cycle | 40% | 50% | 60% | ||
| Rise and fall time | 10% – 90% | 6 | ns | |||
| Jitter | 200 kHz – 10 MHz | 50 | 200 | ps p-p | ||
| Frequency | 23 | 25 | 26 | MHz | ||
| Spread-spectrum clock modulation percentage (Optional) | Center spread | -0.5% | +0.5% | |||
| Down spread | -1% | 0% | ||||
| Spread-spectrum clock modulation frequency (Optional) | 33 | kHz | ||||