JAJSOW0A July   2022  – July 2023 TDP1204

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  4-Level Inputs
      2. 8.2.2  I/O Voltage Level Selection
      3. 8.2.3  HPD_OUT
      4. 8.2.4  Lane Control
      5. 8.2.5  Swap
      6. 8.2.6  Linear and Limited Redriver
      7. 8.2.7  Main Link Inputs
      8. 8.2.8  Receiver Equalizer
      9. 8.2.9  CTLE Bypass
      10. 8.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 8.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 8.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 8.2.12 Input Signal Detect
      13. 8.2.13 Main Link Outputs
        1. 8.2.13.1 Transmitter Bias
        2. 8.2.13.2 Transmitter Impedance Control
        3. 8.2.13.3 TX Slew Rate Control
        4. 8.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 8.2.13.5 TX Swing Control
      14. 8.2.14 DDC Buffer
      15. 8.2.15 HDMI DDC Capacitance
      16. 8.2.16 DisplayPort
    3. 8.3 Device Functional Modes
      1. 8.3.1 MODE Control
        1. 8.3.1.1 I2C Mode (MODE = "F")
        2. 8.3.1.2 Pin Strap Modes
          1. 8.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 8.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ and DDC Buffer Enabled
          3. 8.3.1.2.3 Pin-Strap HDMI 2.1 Function (MODE = "1"): Flexible RX EQ and DDC Buffer Enabled
          4. 8.3.1.2.4 Pin-Strap HDMI 2.1 Function (MODE = "R"): Flexible Rx EQ and DDC Buffer Disabled
      2. 8.3.2 DDC Snoop Feature
        1. 8.3.2.1 HDMI Type
        2. 8.3.2.2 HDMI 2.1 FRL Snoop
      3. 8.3.3 Low Power States
    4. 8.4 Programming
      1. 8.4.1 Pseudocode Examples
        1. 8.4.1.1 HDMI 2.1 Source Example with DDC Snoop and DDC Buffer Enabled
        2. 8.4.1.2 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
      2. 8.4.2 TDP1204 I2C Address Options
      3. 8.4.3 I2C Target Behavior
    5. 8.5 Register Maps
      1. 8.5.1 TDP1204 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Source-Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pre-Channel (LAB)
        2. 9.2.2.2 Post-Channel (LCD)
        3. 9.2.2.3 Common Mode Choke
        4. 9.2.2.4 ESD Protection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Sink-Side Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedures
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Supply Decoupling
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントのサポート
      1. 10.1.1 関連資料
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.8 Receiver Equalizer

The equalizer is used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. TDP1204 supports fixed receiver equalizer by setting the EQ0 and EQ1 pins or through the I2C register. Table 8-6 lists the pin strap settings and EQ values.

The TDP1204 has three sets of CTLE curves (3-Gbps CTLE, 6-Gbps CTLE, and 12-Gbps CTLE) with each curve having 16 AC gain settings and 3 DC gain settings. Table 8-6 provides details about the 16 AC gain settings with GLOBAL_DCG = 0x2.

The TDP1204 in pin-strap mode has three CTLE HDMI Datarate Maps: Map A, Map B, and Map C. Table 8-7 provides details about these maps. The expectation is Map A and C should be used if TDP1204 is used in a source application and Map B for a sink application.

Table 8-8 lists how the sampled state of the CTLEMAP_SEL pin determines the default CTLE HDMI Datarate map when the TDP1204 is configured for pin-strap mode.

In I2C mode, the default CTLE (3-Gbps, 6-Gbps, or 12-Gbps) used for each HDMI mode can be controlled from a register.

Table 8-6 Receiver EQ Settings When GLOBAL_DCG = 0x2
EQ Setting(1) RX EQ Level for 3-Gbps CTLE
(Gain at 1.5-GHz – Gain at 10-MHz)		 RX EQ Level for 6-Gbps CTLE
(Gain at 3-GHz – Gain at 10-MHz)		 RX EQ Level for 12-Gbps CTLE
(Gain at 6-GHz – Gain at 10-MHz)		 EQ1 PIN EQ0 PIN
0(2) 1.0 0.5 0 0 0
1 2.0 1.0 0.8 0 R
2 3.2 2.4 1.8 0 F
3 4.2 3.3 2.7 0 1
4 5.3 4.4 3.7 R 0
5 6.0 5.2 4.4 R R
6 7.0 6.0 5.0 R F
7 7.7 6.8 5.8 R 1
8 9.0 7.5 6.5 F 0
9 9.5 8.2 7.5 F R
10 10.0 8.8 8.3 F F
11 10.5 9.3 9.1 F 1
12 11.0 10.0 9.8 1 0
13 11.5 10.5 10.3 1 R
14 12.0 11.0 11.0 1 F
15 12.3 11.8 11.6 1 1
(1) CLK_EQ, D0_EQ, D1_EQ, and D2_EQ registers determine the receiver EQ setting in I2C mode.
(2) When CTLEBYP_EN = 1 and DCGAIN = 0-dB, EQ settings 0 will be 0-dB due to the CTLE is bypassed.
Table 8-7 CTLE HDMI Datarate Map A, B, and C
HDMI Mode Map A Map B Map C
1.4 12 Gbps CTLE

3 Gbps CTLE

6 Gbps CTLE
2.0 12 Gbps CTLE

6 Gbps CTLE

6 Gbps CTLE
3 Gbps FRL 12 Gbps CTLE

3 Gbps CTLE

6 Gbps CTLE
6 Gbps FRL 12 Gbps CTLE

6 Gbps CTLE

6 Gbps CTLE
8 Gbps FRL 12 Gbps CTLE

12 Gbps CTLE

12 Gbps CTLE
10 Gbps FRL 12 Gbps CTLE

12 Gbps CTLE

12 Gbps CTLE
12 Gbps FRL 12 Gbps CTLE

12 Gbps CTLE

12 Gbps CTLE
Table 8-8 Pin-strap Mode CTLE HDMI Datarate Mapping
Sampled State of CTLEMAP_SEL pin
"0" "R" "F" "1"
CTLE HDMI Datarate Map Map A

Map C

 Map A Map B
Note: The clock lane EQ when operating in HDMI 1.4 or 2.0 will use the 3-Gbps CTLE and will be set to the zero EQ setting.